參數(shù)資料
型號： ST72124J2B7
廠商： 意法半導體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述： 8位單電壓閃存，ADC和16位定時器，SPI和脊髓損傷界面微控制器
文件頁數(shù)： 18/125頁
文件大?。?/td> 776K
代理商： ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
18/125
DATA EEPROM
(Cont’d)
2.6.3 Memory Access
The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart inFigure 8 describesthese different memory
access modes.
Read Operation (LAT=0)
The EEPROM canbe read asa normal ROM loca-
tion when the LAT bit of the EECSR register is
cleared. Ina read cycle, the byte to be accessed is
put on the data bus in less than 1 CPUclock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac-
cording to its address.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter-
rupt is generated if the IE bitis set. The Data EEP-
ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.
Note
: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 8. Data EEPROM ProgrammingFlowchart
READ MODE
LAT=0
PGM=0
WRITE MODE
LAT=1
PGM=0
READ BYTES
IN EEPROM AREA
WRITE UP TO 16 BYTES
IN EEPROM AREA
(with the same 12 MSB of the address)
START PROGRAMMING CYCLE
LAT=1
PGM=1 (set by software)
LAT
INTERRUPT GENERATION
IF IE=1
0
1
CLEARED BY HARDWARE
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相關代理商/技術參數(shù)
參數(shù)描述
ST72124J2B7/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T1/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
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