參數(shù)資料
型號: ST72124J2B7
廠商: 意法半導體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時器,SPI和脊髓損傷界面微控制器
文件頁數(shù): 48/125頁
文件大?。?/td> 776K
代理商: ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
48/125
MISCELLANEOUS REGISTERS
(Cont’d)
6.2.3 Miscellaneous Registers Description
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 =
IS1[1:0]
EI2 and EI3 sensitivity
The interrupt sensitivity, definedusing theIS1[1:0]
bits, is applied to the following external interrupts:
EI2 (port B3..0) and EI3 (port B7..4). These 2 bits
can bewritten only when the I bit of theCC register
is set to 1 (interrupt disabled).
Bit 5 =
MCO
Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(f
OSC
/2 on I/O port)
Note
: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
Bit 4:3 =
IS2[1:0]
EI0 and EI1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied tothe following external interrupts:-
EI0 (port A3..0) and EI1 (port F2..0). These 2 bits
can be writtenonly when theI bit of the CC register
is set to 1 (interrupt disabled).
Bit 2:1 =
CP[1:0]
CPU clock prescaler
These bits select the CPUclock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 0 =
SMS
Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
CPU
=
f
OSC
/ 2
1: Slow mode. f
CPU
is given by CP1, CP0
See low power consumption mode and MCC
chapters for more details.
7
0
IS11
IS10
MCO
IS21
IS20
CP1
CP0
SMS
IS11 IS10
0
0
1
1
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
0
1
0
1
CP1
0
1
0
1
CP0
0
0
1
1
f
CPU
in SLOW mode
f
OSC
/ 4
f
OSC
/ 8
f
OSC
/ 16
f
OSC
/ 32
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