參數(shù)資料
型號(hào)： ST72124J2B7
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述： 8位單電壓閃存，ADC和16位定時(shí)器，SPI和脊髓損傷界面微控制器
文件頁數(shù)： 33/125頁
文件大?。?/td> 776K
代理商： ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
33/125
4.4 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION
CLOCK RESET AND SUPPLY REGISTER
(CRSR)
Read/Write
Reset Value: 000x 000x (00h)
Bit 7:5 =
Reserved
, always read as 0.
Bit 4 =
LVDRF
LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVDis disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 3 =
Reserved
, always read as 0.
Bit 2 =
CSSIE
Clock security syst
.
interrupt enable
This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
CSSIE bit has no effect.
Bit 1 =
CSSD
Clock security system detection
This bit indicates that the safe oscillator of the
Clock SecuritySystem blockhas been selected by
hardware due to a disturbance on the main clock
signal (f
OSC
). It is set by hardware and cleared by
a read of the CRSR register when the original os-
cillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
Bit 0 =
WDGRF
Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or a LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Application notes
In case the LVDRF flag is not cleared upon anoth-
er RESET type occurs (extern or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this condition, a watchdog reset can be detect-
ed by the software while an external reset not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
7
0
0
0
0
LVD
RF
0
CSS
IE
CSS
D
WDG
RF
RESET Sources
LVDRF
WDGRF
External RESET pin
Watchdog
LVD
0
0
1
0
1
X
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
002Bh
CRSR
Reset Value
0
0
0
LVDRF
x
0
CFIE
0
CSSD
0
WDGRF
x
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