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參數(shù)資料
| 型號： | ST72124J2B7 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| 中文描述： | 8位單電壓閃存，ADC和16位定時(shí)器，SPI和脊髓損傷界面微控制器 |
| 文件頁數(shù)： | 72/125頁 |
| 文件大?。?/td> | 776K |
| 代理商： | ST72124J2B7 |
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ST72334J/N, ST72314J/N, ST72124J
72/125
SERIAL PERIPHERAL INTERFACE
(Cont’d)
6.5.4 Functional Description
Figure 46 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
6.5.7for the bit definitions.
6.5.4.1 Master Configuration
In a master configuration, theserial clock is gener-
ated on the SCK pin.
Procedure
– Select theSPR0 & SPR1 bits to define these-
rial clock baud rate (see CR register).
– Select the CPOL and CPHA bits todefine one
of the four relationships between the data
transfer and the serial clock (see Figure 49).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTRand SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. Whenthe DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
2. A write or a read of the DR register.
Note:
While theSPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72124J2B7/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T1/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
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