參數(shù)資料
型號: ST72124J2B7
廠商: 意法半導體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時器,SPI和脊髓損傷界面微控制器
文件頁數(shù): 77/125頁
文件大?。?/td> 776K
代理商: ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
77/125
SERIAL PERIPHERAL INTERFACE
(Cont’d)
6.5.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then theMODF bit isset.
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
Notes:
To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or af-
ter this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODFbit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device canbe in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been amulti-master conflict for system control and
allows a proper exit from systemoperation to a re-
set or default system state using an interrupt rou-
tine.
6.5.4.6 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripher-
al.
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