參數(shù)資料
型號(hào): ST72124J2B7
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時(shí)器,SPI和脊髓損傷界面微控制器
文件頁(yè)數(shù): 26/125頁(yè)
文件大小: 776K
代理商: ST72124J2B7
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ST72334J/N, ST72314J/N, ST72124J
26/125
4.2 RESET SEQUENCE MANAGER (RSM)
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
I
EXTERNAL RESET SOURCE pulse
I
Internal LVD RESET (Low Voltage Detection)
I
Internal WATCHDOG RESET
These sources act on the RESET PIN and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
I
Delay depending on the RESET source
I
4096 CPU clock cycle delay
I
RESET vector fetch
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 14. RESET Sequence Phases
Figure 15. Reset Block Diagram
RESET
DELAY
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
f
CPU
C
RESET
R
ON
V
DD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
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ST72124J2T3 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES