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參數(shù)資料
| 型號： | ST72124J2B7 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| 中文描述： | 8位單電壓閃存，ADC和16位定時器，SPI和脊髓損傷界面微控制器 |
| 文件頁數(shù)： | 39/125頁 |
| 文件大?。?/td> | 776K |
| 代理商： | ST72124J2B7 |
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ST72334J/N, ST72314J/N, ST72124J
39/125
POWER SAVING MODES
(Cont’d)
Standard HALT mode
In this mode the main oscillator is turned off caus-
ing all internal processing to be stopped, including
the operation of the on-chip peripherals. All periph-
erals are not clocked except the ones which get
their clock supply from another clock generator
(such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with Halt
mode is configured by the “WDGHALT” option bit
of the OPTION BYTE. The HALT instruction when
executed while the Watchdog system is enabled,
can generate a Watchdog RESET (see dedicated
section for more details).
When exiting HALT mode by means of a RESET
or an interrupt, the oscillator is immediately turned
on and the 4096 CPU cycle delay is used to stabi-
lize the oscillator.
Specific ACTIVE-HALT mode
As soon as the interrupt capability of the main os-
cillator is selected (OIE bit set), the HALT instruc-
tion will make the device enter a specific ACTIVE-
HALT power saving mode instead of the standard
HALT one.
This mode consists of having only the main oscil-
lator and its associated counter running to keep a
wake-up time base. All other peripherals are not
clocked except the ones which get their clock sup-
ply from another clock generator (such as external
or auxiliary oscillator).
The safeguard against staying locked in this AC-
TIVE-HALT mode is insured by the oscillator inter-
rupt.
Note:
As soon as the interrupt capability of one of
the oscillators is selected (OIE bit set), entering in
ACTIVE-HALT modewhile the Watchdog is active
does not generate a RESET.
This means that the device cannot to spend more
than a defined delay in this power saving mode.
Figure 29. HALT modes flow-chart
HALT
INSTRUCTION
OSCILLATOR
OIE BIT
1
0
CPU
I BIT
OSCILLATOR
PERIPHERALS
ON
OFF
OFF
0
Notes:
CPU
I BIT
OSCILLATOR
PERIPHERALS
OFF
OFF
OFF
0
RESET
EXTERNAL*
INTERRUPT
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS
ON
OFF
OFF
HALT
ACTIVE-HALT
MAIN
FETCH RESET VECTOR
OR SERVICE INTERRUPT**
4096 clock cycles delay
CPU
OSCILLATOR
PERIPHERALS
ON
ON
ON
External interrupt or internal interrupts with Exit from Halt Mode capability
**Before servicing an interrupt, the CC register is pushed on the stack.
*
WATCHDOG
ENABLE
Y
N
If WDGHALT
bit reset in
OPTION BYTE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72124J2B7/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T1/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
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