參數(shù)資料
型號(hào): ST72124J2B7
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時(shí)器,SPI和脊髓損傷界面微控制器
文件頁數(shù): 35/125頁
文件大?。?/td> 776K
代理商: ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
35/125
MAIN CLOCK CONTROLLER
(Cont’d)
MISCELLANEOUS REGISTER 1 (MISCR1)
See section 6.2 on page 47.
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read/Write
Reset Value: 0000 0001 (01h)
Bit 7:4 = Reserved, always read as 0.
Bit 3:2 =
TB1-TB0
Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 =
OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
mode.
When thisbit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Bit 0 =
OIF
Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has measured the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
Warning
: The BRES and BSET instructions must
not be used on the MCCSR register to avoid unin-
tentionally clearing the OIF bit.
Table 5. MCC Register Map and Reset Values
7
0
0
0
0
0
TB1
TB0
OIE
OIF
Counter
Prescaler
Time Base
TB1
TB0
f
OSC
=8MHz
4ms
8ms
20ms
50ms
f
OSC
=16MHz
2ms
4ms
10ms
25ms
32000
64000
160000
400000
0
0
1
1
0
1
0
1
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0029h
MCCSR
Reset Value
0
0
0
0
TB1
0
TB0
0
OIE
0
OIF
1
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