參數(shù)資料
型號： ST72124J2B7
廠商： 意法半導體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述： 8位單電壓閃存，ADC和16位定時器，SPI和脊髓損傷界面微控制器
文件頁數(shù)： 53/125頁
文件大?。?/td> 776K
代理商： ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
53/125
6.4 16-BIT TIMER
6.4.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compareand PWM.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
6.4.2 Main Features
I
Programmableprescaler:f
CPU
dividedby2,4or8.
I
Overflow status flag and maskable interrupt
I
External clock input (must be at least 4 times
slower thantheCPUclockspeed)withthechoice
of active edge
I
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Input capturefunctions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Pulse width modulation mode (PWM)
I
One pulse mode
I
5 alternatefunctionson I/Oports (ICAP1,ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 35.
*Note:
Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
6.4.3 Functional Description
6.4.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte(MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear theTOF bit (overflow
flag), (see note at theend of paragraph titled16-bit
read sequence).
Writing inthe CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of theCR2 register, as illustrated in Table14 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 internal
processorclock cycles depending on the CC1 and
CC0 bits.
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相關代理商/技術參數(shù)
參數(shù)描述
ST72124J2B7/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
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ST72124J2T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T1/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
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