參數(shù)資料
型號: ST72124J2B7
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時器,SPI和脊髓損傷界面微控制器
文件頁數(shù): 66/125頁
文件大?。?/td> 776K
代理商: ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
66/125
16-BIT TIMER
(Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
OC1E
Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode).Whatever the value of theOC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 =
OC2E
Output Compare 2 Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 =
OPM
One Pulse Mode.
0: One Pulse Mode is not active.
1: One PulseMode isactive, theICAP1 pin can be
used totrigger one pulse on the OCMP1 pin;the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 =
PWM
Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Bit 3, 2 =
CC1-CC0
Clock Control.
The value of the timer clock depends on these bits:
Table 14. Clock Control Bits
Bit 1 =
IEDG2
Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 =
EXEDG
External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer Clock
f
CPU
/ 4
f
CPU
/ 2
f
CPU
/ 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
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