參數(shù)資料
型號： ST72124J2B7
廠商： 意法半導體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述： 8位單電壓閃存，ADC和16位定時器，SPI和脊髓損傷界面微控制器
文件頁數(shù)： 81/125頁
文件大?。?/td> 776K
代理商： ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
81/125
SERIAL PERIPHERAL INTERFACE
(Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 =
SPIF
Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
1: Data transfer between the device and an exter-
nal device has been completed.
Note:
While the SPIFbit is set, all writes to the DR
register are inhibited.
Bit 6 =
WCOL
Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 50).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 =
MODF
Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 6.5.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes:
During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value lo-
cated inthe bufferand notthe contents of the shift
register (See Figure 47 ).
7
0
SPIF
WCOL
-
MODF
-
-
-
-
7
0
D7
D6
D5
D4
D3
D2
D1
D0
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
ST72124J2B7/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T1/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
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