參數(shù)資料
型號(hào)： ST72124J2B7
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述： 8位單電壓閃存，ADC和16位定時(shí)器，SPI和脊髓損傷界面微控制器
文件頁(yè)數(shù)： 51/125頁(yè)
文件大?。?/td> 776K
代理商： ST72124J2B7
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ST72334J/N, ST72314J/N, ST72124J
51/125
WATCHDOG TIMER
(Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table12 .Watchdog Timing (fCPU = 8 MHz)):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits containthe number ofincrements
which represents the time delay before the
watchdog produces a reset.
Table 12.Watchdog Timing (f
CPU
= 8 MHz)
Notes:
Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
6.3.4 Hardware Watchdog Option
If Hardware Watchdog Is selected by option byte,
the watchdog is always activeand the WDGA bit in
the CR is not used.
Refer to the device-specific Option Byte descrip-
tion.
6.3.5 Low Power Modes
6.3.6 Interrupts
None.
6.3.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 =
WDGA
Activation bit
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note:
This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 =
T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
STATUS REGISTER (SR)
Read/Write
Reset Value*: 0000 0000 (00h)
Bit 0 =
WDOGF
Watchdog flag
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred
* Only by software and power on/off reset
Note:
This register is not used in versions without
LVD Reset.
CR Register
initial value
FFh
C0h
WDG timeout period
(ms)
98.304
1.536
Max
Min
Mode
WAIT
Description
No effect on Watchdog.
Immediate resetgeneration assoon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
HALT
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
7
0
-
-
-
-
-
-
-
WDOGF
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參數(shù)描述
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ST72124J2T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T1/XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
ST72124J2T3 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
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