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參數(shù)資料
| 型號(hào)： | SIS5595 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Pentium PCI System I/O Chipset |
| 中文描述： | 奔騰的PCI系統(tǒng)I / O芯片 |
| 文件頁數(shù)： | 38/216頁 |
| 文件大?。?/td> | 2208K |
| 代理商： | SIS5595 |
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SiS5595 PCI System I/O Chipset
Preliminary V2.0 Nov. 2, 1998 32 Silicon Integrated Systems Corporation
Since these signals are multiplexed with other signals, the BIOS need to program the
associated bit to select the usage first. Then, the input/output modes for these pins are
further determined if they are selected as GPIO function. While the GPIOx pins are inputs for
the SiS5595, GPI [15:12], GPIO11, and GPIO1 can be set as either edge (falling or rising)
triggered or toggle mode by programming bit [15:11,1] of register 2Ah respectively. The
rising or falling edge depends on the programming of bit [15:11,1] of reg. 24h respectively.
Except these pins, the rest of the GPIO pins are sensitive to level trigger only. The high or
low sensitive mode depends on the programming of bit [17:0] of register 24h respectively.
The default active level is low. While in the input mode, the input level of each GPIO pin can
be directly read back by reading the corresponding bit in the GPIO Pin Status Register
Located in ACPI Register 1Ch. Besides, while in the output mode, the logic of each GPIO pin
can be controlled by writing the desired value to the corresponding bit in the GPIO Pin Status
registers. When configured in the input mode, activation of any of the GPIO[17:7,5:0] pin can
set the corresponding status bit in GPE_STS reg. with a consequence of generating a Power
Management Event (SCI, SMI#, or wake-up event) if the corresponding enable bit of
GPE_EN reg. is set.
For GPIO5, GPO6, and GPIO10, the following rules are supposed to be followed specifically:
1) If GPIO5 and GPIO10 are not adopted, the two pins can not be left open. One external
pull-up or pull-down resistor is required. While GPO6 is not adopted, this pin can be left
open.
2) The three pins are put in high impedance state upon the battery is plugged. The logic is
retained unless it is programmed to serve as other functions. If they are designed as
GPIO function, they can be controllable by appropriate programming, while power is on.
While the system power is down and these pins are programmed to be output mode,
they are rendered to output low state. As a summary of these GPIO pins working at the
GPIO mode, we have to:
Select them working in GPIO function.
Select them functioning in the input/output mode.
Drive output high/or low depending on application.
Note that the bits control the functionality of these multifunction pins, and their input/output
mode are stored in the APC registers. Their logic values are retained as long as the RTC
power exists. For instance, if DUAL_ON#/GPIO5/PME0# is selected to function as GPIO
with input mode, GPIO5 logic will be controlled by setting bit5 of Register 24h in the ACPI I/O
space while the system power is on. While the system power is down, GPIO5 is enforced
high no mater what value has been programmed before. Later when the system power is on
again, GPIO5 stays at output mode with logic controlled by bit 5 of ACPI Register 24h, which
by default is high. For more detail information, please refer to S3 State Related Signals in the
RTC module.
GPIOx Stop and Reload Timers Events
GPIO[17:16, 11:7, 5:1], GPI[15:12] events also can be used to reload PMU standby timer
and stop General Purpose Timer in ACPI. Application software can specify which GPIO
events are able to reload or stop timers (PMU and ACPI) in ACPI registers 2E~2Fh. For
reloading PMU standby timers, bit 3 of 40h, 44h, 48h registers should enable for each timer
in PMU block.
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