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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 9/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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MAILBOX OVERVIEW
S5933
CONFIGURATION
The PCI interface and the Add-On interface each have
four incoming mailboxes (IMBx or AIBMx) and four
outgoing mailboxes (OMBx or AOMBx) along with a
single mailbox status register (MBEF or AMBEF). Out-
going mailboxes are read/write, incoming mailboxes
and the mailbox status registers are read-only.
The following sections discuss the registers associ-
ated with the mailboxes and accesses required for
different modes of mailbox operation.
Mailbox Status
Every byte in each mailbox has a status bit in the
Mailbox Empty/Full Status Registers (MBEF and
AMBEF). Writing a particular byte into an outgoing
mailbox sets the corresponding status bit in both the
MBEF and AMBEF registers. A read of a ‘full’ byte in
a mailbox clears the status bit. The MBEF and
AMBEF are read-only. Status bits cannot cleared by
writes to the status registers.
The S5933 allows the mailbox status bits to be reset
through software. The Bus Master Control/Status
(MCSR) PCI Operation Register and the Add-On Gen-
eral Control/Status (AGCSTS) Add-On Operation Reg-
ister each have a bit to reset mailbox status. Writing a
‘1’ to Mailbox Flag Reset bit in the MCSR or the
AGCSTS register immediately clears all bits in the
both the MBEF and AMBEF registers. Writing a ‘0’ has
no effect. The Mailbox Flag Reset bit is write-only.
The flag bits should be monitored when transferring
data through the mailboxes. Checking the mailbox
status before performing an operation prevents data
from being lost or corrupted. The following se-
quences are suggested for PCI mailbox operations
using status polling (interrupts disabled):
Reading a PCI Incoming Mailbox:
1) Check Mailbox Status. Read the mailbox status register to determine if any information has been
passed from the Add-On interface.
MBEF
Bits 31:16
If a bit is set, valid data is contained in the
corresponding mailbox byte.
2) Read Mailbox(es). Read the mailbox bytes which MBEF indicates are full. This automatically resets
the status bits in the MBEF and AMBEF registers.
IMBx
Bits 31:0
Mailbox data.
Writing a PCI Outgoing Mailbox:
1) Check Mailbox Status. Read the mailbox status register to determine if information previously written
to the mailbox has been read by the Add-On interface. Writes to full mailbox bytes overwrite data
currently in the mailbox (if not already read by the Add-On interface). Repeat until the byte(s) to be
written are empty.
MBEF
Bits 15:0
If a bit is set, valid data is contained in the
corresponding mailbox byte and has not been
read by the Add-On.
2) Write Mailbox(es). Write to the outgoing mailbox byte(s).
OMBx
Bits 31:0
Mailbox data.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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