- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF資料下載
參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 174/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)當(dāng)前第174頁(yè)第175頁(yè)第176頁(yè)
3-109
ADD-ON BUS INTERFACE
S5933
Mailbox Interrupts
Mailboxes can be configured to generate Add-On in-
terrupts (IRQ#) and/or allow the Add-On to generate
PCI interrupts (INTA#). Mailbox empty/full status con-
ditions be can used to interrupt the Add-On or PCI
host to indicate some action is required. An individual
mailbox byte is selected to generate an interrupt
when accessed. An outgoing mailbox becoming
empty or an incoming mailbox becoming full asserts
the interrupt output (if enabled).
When used with a serial nv memory boot device, the
mailboxes also provide a way to generate PCI inter-
rupts (INTA#) through hardware. When a serial nv
memory boot device is used, the device pin functions
EA0 - EA8 are redefined. These pins then provide
direct, external access to the Add-On outgoing mail-
box 4, byte 3 (which is also PCI incoming mailbox 4,
byte 3).
FIFO BUS INTERFACE
The FIFO register on the Add-On interface may be
accessed synchronously or asynchronously.Location
45h, bits 6 and 5 in the nv memory boot device deter-
mine the interface method. If no boot device is used,
the default condition is an asynchronous FIFO inter-
face.
FIFO Direct Access Inputs
RDFIFO# and WRFIFO# are referred to as FIFO ‘di-
rect access’ inputs. Asserting RDFIFO# is function-
ally identical to accessing the FIFO with RD#,
SELECT#, BE[3:0]#, and ADR[6:2]. Asserting
WRFIFO# is functionally identical to accessing the
FIFO with WR#, SELECT#, BE[3:0]#, and ADR[6:2].
RD# and WR# must be deasserted when RDFIFO#
or WRFIFO# is asserted, but SELECT# may be as-
serted. These inputs automatically drive the address
(internally) to 20h and assert all byte enables. The
ADR[6:2] and BE[3:0]# inputs are ignored when us-
ing the FIFO direct access inputs. RDFIFO# and
WRFIFO# are useful for Add-On designs which cas-
cade an external FIFO into the S5933 FIFO or use
dedicated external logic to access the FIFO.
Direct access signals always access the FIFO as 16-
bits or 32-bits, whatever the MODE pin is configured
for. For 16-bit mode, two consecutive accesses fill or
empty the 32-bit FIFO register.
FIFO Status Signals
The FIFO Status signals indicate to the Add-On logic
the current state of the S5933 FIFO. A FIFO status
change caused by a PCI FIFO access is reflected
one PCI clock period after the PCI access is com-
pleted (TRDY# asserted). A FIFO status change
caused by an Add-On FIFO access is reflected im-
mediately (after a short propagation delay) after the
access occurs. For Add-On accesses, FIFO status is
updated after the rising edge of BPCLK for synchro-
nous interfaces or after the rising edge of the read or
write strobe for asynchronous interfaces.
FIFO Control Signals
For Add-On initiated PCI bus mastering, the FIFO
status reset controls FWC# (Add-On to PCI FIFO
clear) and FRC# (PCI to Add-On FIFO clear) are
available. FWC# and FRC# must be asserted for a
minimum of one BPCLK period to be recognized.
These inputs are sampled at the rising edge of BPCLK.
These inputs should not be asserted unless the FIFO is
idle. Asserting a FIFO status reset input during a PCI or
Add-On FIFO access results in indeterminate operation.
For Add-On initiated bus master transfers, AMREN
(Add-On bus master read enable) and AMWEN (Add-
On bus master write enable) are used, in conjunction
with the appropriate FIFO status signals, to enable
the S5933 to assert its PCI bus request (REQ#).
PASS-THRU BUS INTERFACE
The S5933 Pass-Thru interface is synchronous. The
Add-On Pass-Thru Address (APTA) and Add-On
Pass-Thru Data (APTD) registers may be accessed
pseudo-synchronously.
Although BPCLK is used to clock data into and out of
the Pass-Thru registers, accesses may be performed
asynchronously. For reads, APTA or APTD data re-
mains valid as long as RD# (or PTADR#) is asserted.
A new value is not driven until PTRDY# is asserted
by Add-On logic. For writes to APTD, data is clocked
into the S5933 on every BPCLK rising edge, but is
not passed to the PCI bus until PTRDY# is asserted.
PTRDY# must by synchronized to BPCLK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。