參數(shù)資料
型號: S5933QE
廠商: APPLIEDMICRO INC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 4/176頁
文件大?。?/td> 823K
代理商: S5933QE
3-113
ADD-ON BUS INTERFACE
S5933
Timing
Spec.
T = 30 ns
Read cycle time
8T(max)
240 ns
Address valid to data valid
7T–10(max)
200 ns
Address valid to read active
T(max)
30 ns
Read active to data valid
6T–10(max)
170 ns
Read pulse width
6T(max)
180 ns
Data hold from read inactive
2 ns
Memory Device Requirements for Read Accesses
Figure 5. nv Memory Read Operation
Data Valid
EQ[7:0]
(INPUT)
EA[15:0]
(OUTPUT)
ERD#
(OUTPUT)
Address Valid
t35
t36
t37
t39
t38
t41
t40
nv Memory Device Timing Requirements
For serial nv memory devices, the serial clock output
frequency is the PCI clock frequency divided by 512.
This is approximately 65 KHz (with a 33 MHz PCI
clock). Any serial memory device that operates at this
frequency is compatible with the S5933.
For byte-wide accesses, the S5933 generates the
waveforms shown in Figures 5 and 6. Figure 5 shows
an nv memory read operation. Figure 6 shows an nv
memory write operation. Read operations are always
the same length. Write operations, due to the charac-
teristics of reprogrammable nv memory devices, may
be controlled through a programming sequence.
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