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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 24/176頁(yè) |
| 文件大小： | 823K |
| 代理商： | S5933QE |
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3-20
SIGNAL DESCRIPTIONS
S5933
ADD-ON BUS INTERFACE SIGNALS
The following sets of signals represent the interface pins available for the Add-On function. There are four groups:
Register access, FIFO access, Pass-Thru mode pins, and general system pins.
Register Access Pins
DQ[31:00]
t/s
Datapath DQ0–DQ31. These pins represent the datapath for the Add-On peripheral’s
data bus. They provide the interface to the controller’s FIFO and other registers.
When MODE=V
CC, only DQ[15:00] are used. DQ[31:0] have internal pull-up resistors.
ADR[6:2]
in
Add-On Addresses. These signals are the address lines to select which of the 16
DWORD registers within the controller is desired for a given read or write cycle, as
shown in the table below. ADR6 has an internal pull-down resistor.
ADR[6:2]
Register Name
0
0000
Add-On Incoming Mailbox Reg. 1
0
0001
Add-On Incoming Mailbox Reg. 2
0
0010
Add-On Incoming Mailbox Reg. 3
0
0011
Add-On Incoming Mailbox Reg. 4
0
0100
Add-On Outgoing Mailbox Reg. 1
0
0101
Add-On Outgoing Mailbox Reg. 2
0
0110
Add-On Outgoing Mailbox Reg. 3
0
0111
Add-On Outgoing Mailbox Reg. 4
0
1000
Add-On FIFO Port
0
1001
Bus Master Write Address Register
0
1010
Add-On Pass-Thru Address
0
1011
Add-On Pass-Thru Data
0
1100
Bus Master Read Address Register
0
1101
Add-On Mailbox Empty/Full Status
0
1110
Add-On Interrupt Control
0
1111
Add-On General Control/Status Register
1
0110
Bus Master Write Transfer Count
1
0111
Bus Master Read Transfer Count
BE3# or
ADR1
in
Byte Enable 3 (32-bit mode) or ADR1 (16 bit mode). This pin is used in conjunction
with the read or write strobes (RD# or WR#) and the Add-On select signal, SELECT#.
As a Byte Enable, it is necessary to have this pin asserted to perform write operations
to the register identified by ADR[6:2] bit locations d24 through d31; for read operations
it controls the DQ[31:24] output drive. BE3# has an internal pull-up resistor.
BE[2:0]#
in
Byte Enable 2 through 0. These pins provide for individual byte control during register
read or write operations. BE2# controls activity over DQ[23:DQ16], BE1# controls
DQ[15:8], and BE0# controls DQ[7:0]. During read operations they control the output drive
for each of their respective byte lanes; for write operations they serve as a required enable
to perform the modification of each byte lane. BE[2:0]# have internal pull-up resistors.
SELECT#
in
Select for the Add-On interface. This signal must be driven low for any write or read
access to the Add-On interface registers. This signal must be stable during the
assertion of command signals WR# or RD#.
WR#
in
Write strobe. This pin, when asserted in conjunction with the SELECT# pin, causes
the writing of one of the internal registers. The specific register and operand size are
identified through address pins ADR[6:2] and the byte enables, BE[3:0]#.
RD#
in
Read strobe. This pin, when asserted in conjunction with the SELECT# pin, causes
the reading of one of the internal registers. The specific register and operand size are
identified through address pins ADR[6:2] and the byte enables BE[3:0]#.
MODE
in
This pin control whether the S5933 data accesses on the DQ bus are to be 32-bits
wide (MODE = low) or 16-bits wide (MODE = high). When in the 16 bit mode, the
signal BE3# is reassigned as the address signal ADR1. MODE has an internal pull-
down resistor.
Signal
Type
Description
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| S5935 | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
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