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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 169/176頁(yè) |
| 文件大小： | 823K |
| 代理商： | S5933QE |
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3-104
PCI BUS INTERFACE
S5933
PCI BUS INTERRUPTS
The S5933 controller is able to generate PCI bus inter-
rupts by asserting the PCI bus interrupt signal
(INTA#). INTA# is a multisourced, wire-ORed signal
on the PCI bus and is driven by an open drain output
on the S5933. The assertion and deassertion of INTA#
have no fixed timing relationship with respect to the
PCI bus clock. Once the S5933 asserts INTA#, it re-
mains asserted until the interrupt source is cleared by
a write to the Interrupt Control/Status Register
(INTCSR).
PCI BUS PARITY ERRORS
The PCI specification defines two error-reporting sig-
nals, PERR# and SERR#. These signals indicate a
parity error condition on the signals AD[31:0], C/
BE[3:0]#, and PAR. The validity of the PAR signal is
delayed one clock period from its corresponding
AD[31:0] and C/BE[3:0]# signals. Even parity exists
when the total number of ones in the group of signals
is equal to an even number. PERR# is the error-
reporting mechanism for parity errors that occur dur-
ing the data phase for all but PCI Special Cycle
commands. SERR# is the error-reporting mechanism
for parity errors that occur during the address phase.
The timing diagram in Figure 18 shows the timing
relationships between the signals AD[31:0], C/
BE[3:0]#, PAR, PERR# and SERR#.
The S5933 asserts SERR# if it detects odd parity
during an address phase, if enabled. The SERR#
enable bit is bit 8 in the S5933 PCI Command Regis-
ter. The odd parity error condition involves the state
of signals AD[31:0] and C/BE[3:0]# when FRAME# is
first asserted and the PAR signal during the following
clock. If an error is detected, the S5933 asserts
SERR# on the following (after PAR valid) clock.
Since many targets may observe an error on an ad-
dress phase, the SERR# signal is an open drain
multisourced, wire-ORed signal on the PCI bus. The
S5933 drives SERR# low for one clock period when
an address phase error is detected. Once an SERR
error is detected by the S5933, the PCI Status regis-
ter bit 14, System Error, is set and remains until
cleared through software or a hardware reset.
The PERR# signal is similar to the SERR# with two
differences: it reports errors for the data phase and is
only asserted by the device receiving the data. The
S5933 drives this signal (removed from tri-state)
when it is the selected target for write transactions or
when it is the current master for bus read transac-
tions. The parity error conditions are only reflected by
the PERR# pin if the Parity Error Enable bit (bit 6) of
the PCI Command register is set. Upon the detection
of a data parity error, the Detected Parity Error bit (bit
15) of the PCI Status Register is set. Unlike the
PERR# signal pin, this Status bit sets regardless of
the state of the PCI Command register Parity Error
Enable bit. An additional status bit (bit 8) called “Data
Parity Reported” of the PCI Status register is em-
ployed to report parity errors that occur when the
S5933 is the bus master. The “Data Parity Error Re-
ported” status requires that the Parity Error Enable bit
be set in the PCI Command register.
The assertion of PERR# occurs two clock periods
following the data transfer. This two-clock delay oc-
curs because the PAR signal does not become valid
until the clock following the transfer, and an addi-
tional clock is provided to generate and assert
PERR# once an error is detected. PERR# is only
asserted for one clock cycle for each error sensed.
The S5933 only qualifies the parity error detection
during the actual data transfer portion of a data
phase (when both IRDY# and TRDY# are asserted).
Figure 18. Error Reporting Signals
PCI CLOCK
FRAME
AD[31:0]
C/BE[3:0]#
PAR
SERR#
PERR#
12
3
5
4
6
8
7
9
ADDR
DATA
BYTE ENABLES
DATA
BE's
ADDR
A
AA
BB
CMD
READ TRANSACTION
GOOD
WRITE
TRANSACTION
B
A
B
A
B
ERROR
(T)
(I)
(T)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
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相關(guān)代理商/技術(shù)參數(shù) |
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