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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠(chǎng)商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 30/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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3-138
FIFO OVERVIEW
S5933
7) Define transfer byte counts. These registers are
written with the number of bytes to be trans-
ferred. The transfer count does not have to be a
multiple of four bytes. These registers are up-
dated after each transfer to reflect the number of
bytes remaining to be transferred. If transfer
counts are disabled, these registers do not need
to be programmed.
MWTC
All
Write transfer byte count
MRTC
All
Read transfer byte count
8) Enable Bus Mastering. Once steps 1-7 are com-
pleted, the FIFO may operate as a PCI bus mas-
ter. Read and write bus master operation may be
independently enabled or disabled. The AMREN
and AMWEN inputs control bus master enabling
for Add-On initiated bus mastering. The MCSR
bus master enable bits are ignored for Add-On
initiated bus mastering.
It is recommended that bus mastering be enabled as
the last step. Some applications may choose to leave
bus mastering enabled (AMREN and AMWEN as-
serted) and start transfers by writing a non-zero value
to the transfer count registers (if they are enabled).
If interrupts are enabled, an Add-On CPU interrupt
service routine is also required. The service routine
determines the source of the interrupt and resets the
interrupt. As mailbox registers may also be config-
ured to generate interrupts, the exact source of the
interrup is indicated in the Add-On Interrupt Control
Register (AINT). Typically, the interrupt service rou-
tine is used to setup the next transfer by writing new
addresses and transfer counts (if enabled), but some
applications may also require other actions. If read
transfer or write transfer complete interrupts are en-
abled, the master/target abort interrupt is automati-
cally enabled. These indicate a transfer error has
occurred. Writing a one to these bits clears the corre-
sponding interrupt.
AINT
Bit 21
Master/target abort caused
interrupt
AINT
Bit 19
Read transfer complete
caused interrupt
AINT
Bit 18
Write transfer complete
caused interrupt
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
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