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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 22/176頁(yè) |
| 文件大小： | 823K |
| 代理商： | S5933QE |
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3-131
FIFO OVERVIEW
S5933
FIFO PCI Bus Master Reads
For PCI read transfers (filling the PCI to Add-On
FIFO), read cycles are performed until one of the
following occurs:
– Bus Master Read Transfer Count Register
(MRTC), if used, reaches zero
– The PCI to Add-On FIFO is full
– GNT# is removed by the PCI bus arbiter
– AMREN is deasserted
If the transfer count is not zero, GNT# remains as-
serted, and AMREN is asserted, the FIFO continues
to read data from the PCI bus until there are no
empty locations in the PCI to Add-On FIFO. If the
Add-On can empty the FIFO as quickly as it can be
filled from the PCI bus, very long bursts are possible.
The S5933 deasserts REQ# when it completes the
access to fill the last location in the FIFO. Once
REQ# is deasserted, it will not be reasserted until the
FIFO management condition is met.
FIFO PCI Bus Master Writes
For PCI write transfers (emptying the Add-On to PCI
FIFO), write cycles are performed until one of the
following occurs:
– Bus Master Write Transfer Count Register
(MWTC), if used, reaches zero
– The Add-On to PCI FIFO is empty
– GNT# is removed by the PCI bus arbiter
– AMWEN is deasserted
If the transfer count is not zero, GNT# remains as-
serted, and AMWEN is asserted, The FIFO continues
to write data to the PCI bus until there are is no data in
the Add-On to PCI FIFO. If the Add-On can fill the FIFO
as quickly as it can be emptied to the PCI bus, very
long bursts are possible. The S5933 deasserts REQ#
when it completes the access to transfer the last data in
the FIFO. Once REQ# is deasserted, it will not be reas-
serted until the FIFO management condition is met.
Add-On Bus Interface
The FIFO register may be accessed in two ways from
the Add-On interface. It can be accessed through
normal register accesses or directly with the
RDFIFO# and WRFIFO# inputs. In addition, the FIFO
register can be accessed with synchronous or asyn-
chronous to BPCLK, depending on the S5933 con-
figuration. The Add-On interface also supports
datapaths which are not 32-bits. The method used to
access the FIFO from the Add-On interface is inde-
pendent of whether the FIFO is a PCI PCI target or a
PCI initiator.
Add-On FIFO Register Accesses
The FIFO may be accessed from the Add-On interface
through the Add-On FIFO Port Register (AFIFO) read
or write. This is offset 20h in the Add-On Operation
Registers. Depending on the device configuration, this
register can be accessed either synchronous BPCLK
or asynchronous to BPCLK. To access the FIFO as a
normal Add-On Operation Register, ADR[6:2],
BE[3:0]#, SELECT#, and RD# or WR# are required.
The major differences between synchronous and
asynchronous modes are when the FIFO pointers ad-
vance and the ability to perform burst accesses. The
following examples are shown for Add-On FIFO reads.
Figure 7 shows an asynchronous FIFO register read.
SELECT# must meet setup and hold times relative to
the rising edge of RD#. RD# and SELECT# both as-
serted enables the DQ outputs, and the first data
location in the FIFO is driven onto the bus. The FIFO
address and the byte enables must be valid before
valid data is driven onto the DQ bus. Data remains
valid as long as the address, byte enables, SELECT#
and RD# are asserted. Deasserting RD# or SE-
LECT# causes the data bus to float. The rising edge
of RD# causes the FIFO pointer to advance. The
status outputs are updated to reflect the FIFO condi-
tion after it advances.
Figure 7. Asynchronous FIFO Register Read Access Example
BE[3:0]#
ADR[6:2]
DQ[31:0]
SELECT#
RD#
RDEMPTY
Valid Byte Enables
Valid Address
Valid Data
Status Before Read
New Status
FIFO Pointer Advances
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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