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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 44/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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3-151
PASS-THRU OVERVIEW
S5933
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 2: SELECT#, byte enables, and the address
inputs remain driven to read the Pass-Thru
Data Register at offset 2Ch. PTBURST# is
asserted by the S5933, indicating the
current Pass-Thru read is a burst.
Clock 3: WR# asserted at the rising edge of clock 3
writes DATA 1 into the S5933. PTRDY#
asserted at the rising edge of clock 3
completes the current data phase.
Clock 4: WR# asserted at the rising edge of clock 4
writes DATA 2 into the S5933. PTRDY#
asserted at the rising edge of clock 4
completes the current data phase.
Clock 5: WR# asserted at the rising edge of clock 5
writes DATA 3 into the S5933. PTRDY#
asserted at the rising edge of clock 5
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. This is
how a PCI initiator adds wait states, if it
cannot read data quickly enough.
Clock 6: PTATN# remains deasserted at the rising
edge of clock 6. The Add-On cannot write
DATA 4 until PTATN# is asserted. PTATN#
is reasserted during the cycle, indicating the
PCI initiator is no longer adding wait states.
Add-On logic continues to drive DATA 4 on
the Add-On bus.
Clock 7: WR# asserted at the rising edge of clock 7
writes DATA 4 into the S5933. PTRDY#
asserted at the rising edge of clock 7
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. The
PCI initiator is adding wait states.
Clock 8: PTATN# remains deasserted at the rising
edge of clock 8. The Add-On cannot write
DATA 5 until PTATN# is asserted. Add-On
logic continues to drive DATA 5 on the
Add-On bus.
Clock 9: PTATN# remains deasserted at the rising
edge of clock 9. The Add-On cannot write
DATA 5 until PTATN# is asserted. Add-On
logic continues to drive DATA 5 on the
Add-On bus. PTATN# is reasserted during
the cycle, indicating the PCI initiator is
done adding wait states.
Clock 10: WR# asserted at the rising edge of clock
10 writes DATA 5 into the S5933. PTRDY#
asserted at the rising edge of clock 10
completes the current data phase.
Clock 11: WR# asserted at the rising edge of clock
11 writes DATA 6 into the S5933. PTRDY#
asserted at the rising edge of clock 11
completes the final data phase.
Clock 12: PTBURST# is deasserted at the rising
edge of clock 12 indicating the Pass-Thru
burst is complete. The S5933 can accept
new Pass-Thru accesses from the PCI bus
at clock 14. Any data written into the Pass-
Thru data register is not required and is
never passed to the PCI interface (as
PTRDY# is not asserted at the rising edge
of clock 13).
Figure 7 also shows a 5 data phase Pass-Thru burst
read, but the Add-On logic uses PTRDY# to control
the rate at which data is transferred. In many applica-
tions, Add-On logic is not fast enough to provide data
every BPCLK (every 30 ns in a 33 MHz PCI system).
In this example, the Add-On interface writes data ev-
ery other clock cycle. WR# is shown asserted during
the entire Add-On burst, but WR# can be deasserted
when PTRDY# is deasserted, the S5933 functions
the same under both conditions.
Clock 0: PCI address information is stored in the S5933
Pass-Thru Address Register. The PCI
address is recognized as an access to Pass-
Thru region 1. PTATN# is asserted by the
S5933 to indicate a Pass-Thru access is
occurring.
Clock 1: Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 2.
PTBURST#
Deasserted, the S5933 does
not yet recognize a PCI
burst.
PTNUM[1:0] 01. Indicates the PCI access
is to Pass-Thru region 1.
PTWR
Deasserted. The Pass-Thru
access is a read.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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| S59355QRC | 制造商:AppliedMicro 功能描述: |
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| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
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