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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 37/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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PASS-THRU OVERVIEW
S5933
The Add-On PTADR# input directly accesses the
Pass-Thru Address Register and drives the contents
onto the data bus (no BPCLK rising edge is re-
quired). The byte enables, address, and SELECT#
inputs are ignored when PTADR# is asserted. RD#
and WR# must not be asserted when PTADR# is
asserted.
Clock 0: The PCI bus cycle address is stored in the
S5933 Pass-Thru Address Register.
Clock 1: The PCI address is recognized as an
access to Pass-Thru region 1. PCI data is
stored in the S5933 Pass-Thru Data
Register. PTATN# is asserted to indicate a
Pass-Thru access is occurring.
Clock 2: Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 2.
PTBURST#
Deasserted. The access has
a single data phase.
PTNUM[1:0] 01. Indicates the PCI access
is to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru
access is a write.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 3: SELECT#, byte enable, and the address
inputs remain valid to read the Pass-Thru
Data Register at offset 2Ch. RD# is
asserted to drive data register contents
onto the DQ bus.
Clock 4: If PTRDY# is asserted at the rising edge of
clock 4, PTATN# is immediately deasserted
and the Pass-Thru access is completed at
clock 5.
Clock 5: If Add-On logic requires more time to read
the Pass-Thru Data Register (slower
memory or peripherals), PTRDY# can be
delayed, extending the cycle. PTRDY#
asserted at the rising edge of clock 5 causes
PTATN# to be immediately deasserted.
Clock 6: PTATN# and PTBURST# deasserted at
the rising edge of clock 6 indicates the
Pass-Thru access is complete. The S5933
can accept new Pass-Thru accesses from
the PCI bus at clock 7.
Single Cycle Pass-Thru Reads
A single cycle Pass-Thru read operation occurs when
a PCI initiator reads a single value from a Pass-Thru
region. PCI single cycle transfers consists of an ad-
dress phase and a one data phase. During the ad-
dress phase of the PCI transfer, the S5933 stores the
PCI address into the Pass-Thru Address Register
(APTA). If the S5933 determines that the address is
within one of its defined Pass-Thru regions, it indi-
cates to the Add-On that a write to the Pass-Thru
Data Register (APTD) is required.
Figure 3 shows a single cycle Pass-Thru read access
(Add-On write) using PTADR#. The Add-On reads
data from a source on the Add-On and writes it to the
APTD register.
Clock 0: PCI address information is stored in the
S5933 Pass-Thru Address Register. The PCI
cycle is recognized as an access to Pass-
Thru region 1. PTATN# is asserted by the
S5933 to indicate a Pass-Thru access is
occurring.
Clock 1: Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 1.
PTBURST#
Deasserted. The access has
a single data phase.
PTNUM[1:0] 01. Indicates the PCI access
was to Pass-Thru region 1.
PTWR
Deasserted. The Pass-Thru
access is a read.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 2: This clock is required to avoid contention
on the DQ bus. Time must be allowed after
PTADR# is deasserted for the DQ outputs
to float before Add-On logic attempts to
write to the Pass-Thru Data Register.
Clock 3: SELECT#, byte enables, and the address
inputs remain valid to write the Pass-Thru
Data Register at offset 2Ch. If WR# is
asserted at the rising edge of clock 3, data
on the DQ bus is latched into APTD.
If PTRDY# is asserted at the rising edge of
clock 3, PTATN# is immediately deasserted
and the Pass-Thru access is completed at
clock 4.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| S5935 | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
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