- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF資料下載
參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠(chǎng)商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 26/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)
3-134
FIFO OVERVIEW
S5933
reset the PCI to Add-On or Add-On to PCI FIFO
flags. The FIFO flags can always be reset with soft-
ware through the Add-On General Control/Status
Register (AGCSTS) or the Bus Master Control/Status
Register (MCSR), but these hardware inputs are use-
ful for designs which do no implement a CPU on the
Add-On card. Asserting the FRC# input resets the
PCI to Add-On FIFO. Asserting the FWC# input re-
sets the Add-On to PCI FIFO.
The AMREN and AMWEN inputs allow Add-On logic to
individually enable and disable bus mastering for the
PCI to Add-On and Add-On to PCI FIFO. These inputs
override the Bus Master Control/Status Register
(MCSR) bus master enable bits. The S5933 may re-
quest the PCI bus for the PCI to Add-On FIFO when
AMREN is asserted and may request the PCI bus for
the Add-On to PCI FIFO when AMWEN is asserted. If
AMREN or AMWEN is deasserted, the S5933 removes
its PCI bus request and gives up control of the bus.
AMREN and AMWEN are useful for Add-Ons with
external FIFOs cascaded into the S5933. For PCI
bus master write operations, the entire S5933 Add-
On to PCI FIFO and the external FIFO may be filled
before enabling bus mastering, providing a single
long burst write rather than numerous short bursts.
In some applications, the amount of data to be trans-
ferred is not known. During read operations, the
S5933, attempting to fill its PCI to Add-On FIFO, may
access up to eight memory locations beyond what is
required by the Add-On before it stops. In this situa-
tion, AMREN can be deasserted to disable PCI
reads, and then FRC# can be asserted to flush the
unwanted data from the FIFO.
FIFO Generated Add-On Interrupts
For Add-On initiated bus mastering, the S5933 may
be configured to generate interrupts to the Add-On
interface for the following situations:
– Read transfer count reaches zero
– Write transfer count reaches zero
– An error occurred during the bus master trans-
action
The interrupt is posted to the Add-On interface with
the IRQ# output. A high-to-low transition on this out-
put indicates an interrupt condition. Because there is
a single interrupt output and multiple interrupt condi-
tions, the Add-On Interrupt Control/Status Register
(AINT) must be read to determine the interrupt
source. This register is also used to clear the inter-
rupt, returning IRQ# to its high state. If mailbox inter-
rupts are also used, this must be considered in the
interrupt service routine.
8-Bit and 16-Bit FIFO Add-On Interfaces
The S5933 FIFO may also be used to transfer data
between the PCI bus and 8-bit or 16-bit Add-On inter-
faces. This can be done using FIFO advance condi-
tions or the S5933 MODE input pin.
The FIFO may be used as an 8-bit or 16-bit wide
FIFO. To use the FIFO as an 8-bit interface, the ad-
vance condition should be set for byte 0 (no data is
transferred in the upper 3 bytes). To use the FIFO as
a 16-bit interface, the advance condition should be
set for byte 1 (no data is transferred in the upper 2
bytes). This allows a simple Add-On bus interface,
but it has the disadvantage of not efficiently utilizing
the PCI bus bandwidth because the host is forced to
perform 8-bit or 16-bit accesses to the FIFO on the
PCI bus. This is the only way to communicate with an
8-bit Add-On through the FIFO without additional
logic to steer byte lanes on the Add-On data bus.
Pass-Thru mode is more suited to 8-bit Add-On inter-
faces.
Implementing a 16-bit wide FIFO is a reasonable so-
lution, but to avoid wasting PCI bus bandwidth, the
best method is to allow the PCI bus and the FIFO to
operate with 32-bit data. The S5933 can assemble or
disassemble 32-bit quantities for the Add-On inter-
face. This is possible through the MODE pin. When
MODE is low, the Add-On data bus is 32-bits. When
MODE is high, the Add-On data bus is 16-bits. When
MODE is configured for 16-bit operation, BE3# be-
comes ADR1.
With the FIFO direct access signals (RDFIFO# and
WRFIFO#), the MODE pin must reflect the actual
Add-On data bus width. With MODE = 16-bits, the
S5933 automatically takes two consecutive, 16-bit
Add-On writes to the FIFO and assembles a 32-bit
value. FIFO reads operate in the same manner. Two
consecutive Add-On reads empty the 32-bit FIFO
register. The 16-bit data bus is internally steered to
the lower and upper words of the 32-bit FIFO register.
One consideration needs to be taken when using the
FIFO direct access signals and letting the S5933 do
byte lane steering internally. The default condition
used to advance the FIFO is byte 0. This must be
changed to byte 2 or 3. When MODE is configured
for a 16-bit Add-On bus, the first 16-bit cycle to the
FIFO always accesses the low 16-bits. If the FIFO
advance condition is left at byte 0, the FIFO ad-
vances after the first 16-bit cycle and the data in the
upper 16-bits is directed to the next FIFO location,
shifting the data.
The FRC# and FWC# inputs allow Add-On logic to
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。