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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 98/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
12-18
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
to the initiator with TRDY# (completing the cycle).
FRAME# could remain asserted, indicating a burst
read, but the retry request conditions are identical for
a single data phase read and the first data phase of a
burst read.
BPCLK is identical to PCICLK, lagging by a propaga-
tion delay of a few nanoseconds (see Chapter 13).
PTATN# is asserted on the Add-On interface as soon
as FRAME# is sampled active at a PCICLK rising
edge.
After PTATN# is asserted, PTRDY# must be as-
serted by the 15th BPCLK rising edge to prevent the
S5933 from requesting a retry. TRDY# is asserted on
the PCI interface one clock cycle after PTRDY# is
asserted on the Add-On interface. If Add-On logic
does not return PTRDY# by the 15th BPCLK rising
edge, the S5933 asserts STOP#, requesting a retry
from the PCI initiator.
For Pass-Thru write operations, the S5933 never dis-
connects on the first or second PCI data phases of a
burst. The first data and second phases are always
accepted immediately by the S5933. No further ac-
tion is required by the PCI initiator. The only situation
where the S5933 may respond to a Pass-Thru write
with a retry request is after the second data phase of
a Pass-Thru burst write.
Figure 12-9 shows the conditions required for the
S5933 to request a retry after the second data phase
of a burst transfer. This figure applies to both Pass-
Thru burst read and write operations.
The previous data phase is completed with the asser-
tion of PTRDY# at the rising edge of BPCLK 0. Add-
On logic must assert PTRDY# by the rising edge of
BPCLK 8 to prevent the S5933 from asserting
STOP#, requesting a retry. Meeting this condition al-
lows the S5933 to assert TRDY# by the rising edge
of PCICLK 8, completing the data phase with requir-
ing a retry.
When the S5933 requests a retry, the Pass-Thru sta-
tus indicators remain valid (allowing the Add-On logic
to complete the access). PTBURST# is the exception
to this. PTBURST# is deasserted to indicate that
there is currently no burst in progress on the PCI bus.
The other Pass-Thru status indicators remain valid
until PTATN# is deasserted. Figure 12-10 shows the
Add-On bus interface signals after the S5933 re-
quests a retry.
As long as PTATN# remains asserted, Add-On logic
should continue to transfer data. For PCI read opera-
tions, one Add-On write operation is required after a
retry request. After the Add-On write, asserting
PTRDY# deasserts PTATN#.
For Pass-Thru write operations, one or two data
transfers may remain after the S5933 signals a retry.
Two data transfers are possible because the S5933
has a double buffered Pass-Thru data register used
for writes. A PCI burst may have filled both registers
before the S5933 requested a retry. PTATN# re-
mains asserted until both are emptied. PTRDY# must
be asserted after each read from the Pass-Thru data
register. If both registers are full, PTATN# is
deasserted only after PTRDY# is asserted the sec-
ond time. The S5933 only accepts further PCI ac-
cesses after both registers are emptied.
12.2.2.6 8-Bit and 16-Bit Pass-Thru Add-On
Bus Interface
The S5933 allows a simple interface to devices with
8-bit or 16-bit data buses. Each Pass-Thru region
may be defined as 8-, 16-, or 32-bits, depending on
the contents of the nv memory boot device loaded
into the PCI Base Address Configuration Registers
during initialization (Section 12.3.2). The Pass-Thru
Add-On interface internally controls byte lane steer-
ing to allow access to the 32-bit Pass-Thru Data Reg-
ister (APTD) from 8-bit or 16-bit Add-On buses.
Figure 12-9. Target Requested Retry after the First Data Phase of a Burst Operation
8
7
6
1
9
8
7
2
1
0
PCICLK
FRAME#
STOP#
BPCLK
PTATN#
PTRDY#
Latest assertion of PTRDY#
to prevent disconnect
PTRDY# asserted too late,
results in disconnect
PCI Data Transfer
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