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參數(shù)資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 155/327頁 |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-11
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
3.4
FIFO Management Schemes
The S5933 provides flexibility in how the FIFO is man-
aged for DMA transfers. The FIFO management
scheme determines when the S5933 requests the
PCI bus (asserts REQ#). The most efficient way to
untilize the capabilities of the PCI bus is with burst
transfers. Requesting the PCI bus every time the
FIFO contains a single double-word is an ineffecient
use of the bus, and limits the performance of other
PCI devices within a system. It is more desirable re-
quest the bus when multiple operations are required,
allowing the S5933 to perform a burst transfer.
The management scheme is configurable for the PCI
to add-on and add-on to PCI FIFOs (and may be
different for each). Bus mastering must be enabled
for the management scheme to apply (via the MCSR
enable bits or AMREN/AMWEN). The FIFO manage-
ment option is programmed through the Bus Master
Control/Status Register (MCSR).
For the PCI to add-on FIFO (DMA reads), there are
two options. The FIFO can be programmed to request
the bus when any FIFO location is empty or only
when four or more locations are empty. After the
S5933 is granted control of the PCI bus, the manage-
ment scheme does not apply. The device continues to
read as long as there is an open FIFO location. For
DMA read transfers, the S5933 maintains control of
the PCI bus until one of the following events:
The read transfer count (MRTC) reaches
zero
Bus mastering is disabled (with the MSCR
enable bit or AMREN)
Another master requests the bus and the
Latency Timer is expired
The PCI target aborts the transfer
The PCI to add-on FIFO becomes full
For the add-on to PCI FIFO (DMA writes), there are
two management options. The FIFO can be pro-
grammed to request the bus when any FIFO location
is full or only when four or more locations are full.
After the S5933 is granted control of the PCI bus, the
management scheme does not apply. The device
continues to write as long as there is data in the FIFO.
For DMA write transfers, the S5933 maintains control
of the PCI bus until one of the following events:
The write transfer count (MWTC) reaches zero
Bus mastering is disabled (with the MSCR
enable bit or AMWEN)
Another master requests the bus and the
Latency Timer is expired
The PCI target aborts the transfer
The add-on to PCI FIFO becomes empty
There are two special cases for the add-on to PCI
FIFO management scheme. The first case is when
the FIFO is programmed to request the PCI bus only
when four or more locations (16 bytes) are full, but
the transfer count is less than 16 bytes. In this situa-
tion, the FIFO ignores the management scheme and
finishes transferring the data. The second case is
when the S5933 is configured for add-on initiated
bus mastering. In this situation, the FIFO manage-
ment scheme must be set to request the PCI bus
when one or more locations are full.
3.5
S5933 DMA Channel Priority
In many applications, the S5933 performs both DMA
read and write transfers. This requires a priority
scheme be implemented between the two FIFOs. If
the FIFO management condition for initiating a PCI
read and a PCI write are both met, a method must
exist to determine which transfer is performed first.
Bits D12 and D8 in the Bus Master Control/Status
Register (MCSR) control the read and write DMA
channel priority, respectively. If these bits are both
set or both clear, priority alternates, beginning with
read transfers. If the read priority is set and the write
priority is clear, read cycles take priority. If the write
priority is set and the read priority is clear, write
cycles take priority. Priority arbitration is only done
when neither FIFO has control of the PCI bus (the
PCI to add-on FIFO never interrupts an add-on to
PCI FIFO transfer in progress and vice-versa).
3.6
S5933 DMA Interrupts
The S5933 can generate interrupts under the follow-
ing conditions: the read transfer count reaches zero,
the write transfer count reaches zero, or an error
occurs on the PCI bus during a DMA transfer.
Which interface (PCI bus or add-on bus) receives the
interrupt is determined by which side initiated the
DMA transfer. If PCI initiated DMA transfers are used,
a PCI INTA# interrupt is generated when an interrupt
condition is met. If add-on initiated DMA transfers are
used, IRQ# is generated to the add-on interface. In-
terrupts are optional and may be disabled.
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