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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 42/327頁(yè) |
| 文件大小： | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
9-7
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
9.2.1 Mailbox Interrupts
Mailboxes can be configured to generate Add-On in-
terrupts (IRQ#) and/or allow the Add-On to generate
PCI interrupts (INTA#). Mailbox empty/full status con-
ditions be can used to interrupt the Add-On or PCI
host to indicate some action is required. An individual
mailbox byte is selected to generate an interrupt
when accessed. An outgoing mailbox becoming
empty or an incoming mailbox becoming full asserts
the interrupt output (if enabled).
When used with a serial nv memory boot device, the
mailboxes also provide a way to generate PCI inter-
rupts (INTA#) through hardware. When a serial nv
memory boot device is used, the device pin functions
EA0 - EA8 are redefined. These pins then provide
direct, external access to the Add-On outgoing mail-
box 4, byte 3 (which is also PCI incoming mailbox 4,
byte 3). See Section 10.1.3 for details.
9.3
FIFO BUS INTERFACE
The FIFO register on the Add-On interface may be
accessed synchronously using the method described
in section 9.1.2 or asynchronously using the method
described in Section 9.1.3. Location 45h, bits 6 and 5
in the nv memory boot device determine the interface
method (see Section 11.3.1). If no boot device is
used, the default condition is an asynchronous FIFO
interface.
9.3.1 FIFO Direct Access Inputs
RDFIFO# and WRFIFO# are referred to as FIFO ‘di-
rect access’ inputs. Asserting RDFIFO# is function-
ally identical to accessing the FIFO with RD#,
SELECT#, BE[3:0]#, and ADR[6:2]. Asserting
WRFIFO# is functionally identical to accessing the
FIFO with WR#, SELECT#, BE[3:0]#, and ADR[6:2].
RD# and WR# must be deasserted when RDFIFO#
or WRFIFO# is asserted, but SELECT# may be as-
serted. These inputs automatically drive the address
(internally) to 20h and assert all byte enables. The
ADR[6:2] and BE[3:0]# inputs are ignored when us-
ing the FIFO direct access inputs. RDFIFO# and
WRFIFO# are useful for Add-On designs which cas-
cade an external FIFO into the S5933 FIFO or use
dedicated external logic to access the FIFO.
Direct access signals always access the FIFO as 16-
bits or 32-bits, whatever the MODE pin is configured
for. For 16-bit mode, two consecutive accesses fill or
empty the 32-bit FIFO register (see Section 11.2.3.5).
9.3.2 FIFO Status Signals
The FIFO Status signals (Section 11.1.2) indicate to
the Add-On logic the current state of the S5933
FIFO. A FIFO status change caused by a PCI FIFO
access is reflected one PCI clock period after the PCI
access is completed (TRDY# asserted). A FIFO sta-
tus change caused by an Add-On FIFO access is
reflected immediately (after a short propagation de-
lay) after the access occurs. For Add-On accesses,
FIFO status is updated after the rising edge of
BPCLK for synchronous interfaces or after the rising
edge of the read or write strobe for asynchronous
interfaces (See Chapter 13 for exact timings).
9.3.3 FIFO Control Signals
For Add-On initiated PCI bus mastering, the FIFO
status reset controls FWC# (Add-On to PCI FIFO
clear) and FRC# (PCI to Add-On FIFO clear) are
available. FWC# and FRC# must be asserted for a
minimum of one BPCLK period to be recognized.
These inputs are sampled at the rising edge of BPCLK.
These inputs should not be asserted unless the FIFO is
idle. Asserting a FIFO status reset input during a PCI or
Add-On FIFO access results in indeterminate operation.
For Add-On initiated bus master transfers (Section
11.2.3.3), AMREN (Add-On bus master read enable)
and AMWEN (Add-On bus master write enable) are
used, in conjunction with the appropriate FIFO status
signals, to enable the S5933 to assert its PCI bus
request (REQ#).
9.4
PASS-THRU BUS INTERFACE
The S5933 Pass-Thru interface is synchronous. The
Add-On Pass-Thru Address (APTA) and Add-On
Pass-Thru Data (APTD) registers may be accessed
pseudo-synchronously using the method described in
Section 9.1.3.
Although BPCLK is used to clock data into and out of
the Pass-Thru registers, accesses may be performed
asynchronously. For reads, APTA or APTD data re-
mains valid as long as RD# (or PTADR#) is asserted.
A new value is not driven until PTRDY# is asserted
by Add-On logic. For writes to APTD, data is clocked
into the S5933 on every BPCLK rising edge, but is
not passed to the PCI bus until PTRDY# is asserted.
PTRDY# must by synchronized to BPCLK.
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