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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 158/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-13
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
Bit 19 Read Transfer Complete Interrupt.
When set, this bit indicates MRTC has
decremented to zero and IRQ# has been
asserted. Writing a one to this bit clears
the interrupt source and deasserts IRQ#.
Writing a zero to this bit has no effect.
Bit 21 Bus Master Error Interrupt. When set,
this bit indicates that the S5933 had to
perform a master abort or received a
target abort and IRQ# has been asserted.
Writing a one to this bit clears the inter-
rupt source and deasserts IRQ#. Writing
a zero to this bit has no effect.
3.6.4
PCI Interrupt Considerations
If the S5933 is configured to generate PCI bus inter-
rupts (INTA#) for DMA transfer counts and PCI bus
error conditions, considerations must be made for
the interrupt handler. The interrupt vector must be
obtained, and because hardware interrupts may be
shared, interrupt handlers may have to be “chained.”
3.6.4.1
Enabling PCI Interrupts
The Interrupt Pin (INTFIN) PCI Configuration Regis-
ter may be loaded out of non-volatile memory offset
7Dh by the S5933 at reset. The value loaded into
this register identifies which PCI interrupt: INTA#,
INTB#, INTC#, or INTD# is used. The default value
is 01h, identifying INTA#. For the S5933, the INTA#
output should be connected to the PCI bus INTA# pin.
If PCI interrupts are not required, this register may be
initialized to 00h (interrupts disabled) or ignored.
The four PCI interrupts are mapped within the system
chipset to standard PC IRQ numbers (0-15). The
82C59A compatible interrupt controllers (two cas-
caded controllers) each have an interrupt mask regis-
ter. The master mask register, located at system I/O
location 21h controls the masking of IRQ0-7, and the
slave mask register, located at system I/O location
1Ah controls the masking of IRQ8-15. Application
software must make sure the S5933 interrupt line (in-
dicated by the PCI Interrupt Line Register described
in Section 3.6.4.2) is unmasked. If the interrupt is
masked, the handler never executes.
3.6.4.2
PCI Host Interrupt Handlers
The S5933 Interrupt Line (INTLN) PCI Configuration
Register is loaded out of non-volatile memory offset 7Ch
by the S5933 at reset. The value loaded into the register
is a hardware interrupt number for the host interrupt
controller (IRQ0 to 15). This value may be used by the
host, or the BIOS may overwrite it with its own value.
Multiple PCI devices may be assigned to a single
hardware interrupt by the host. PCI device drivers
are, therefore, required to determine if the current
interrupt was generated by the device it services. If
not, it must pass control, or “chain” the previous in-
terrupt handler to service the interrupt.
Each application’s code must install its own interrupt
vector. To do this, the Interrupt Line Configuration Reg-
ister is read. A value between 0 and 15 is returned,
corresponding to a PC hardware IRQ number. This
must be translated into a software interrupt number.
The following table shows the conversions for a PC:
Hardware Interrupt Software Interrupt
IRQ0
08h
IRQ1
09h
IRQ2
0Ah
IRQ3
0Bh
IRQ4
0Ch
IRQ5
0Dh
IRQ6
0Eh
IRQ7
0Fh
IRQ8
70h
IRQ9
71h
IRQ10
72h
IRQ11
73h
IRQ12
74h
IRQ13
75h
IRQ14
76h
IRQ15
77h
Once the software interrupt number is calculated,
the previous interrupt handler’s vector can be read
and stored. The new interrupt vector is then in-
stalled. In this manner, numerous devices within a
system can share a single hardware interrupt.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PCI Product |
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