
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-31
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933
Figure 3. DMA Controller Add-on Bus Master State Machine
The MASTER 4 data phase can be entered from either the address phase (if the transfer count has
decremented to 12) or from MASTER 3. During the MASTER 4 data phase, RDY_IN# and STOP are monitored.
STOP is an internal signal which is asserted when a DMA request goes inactive. For example, if the last double-
word in the PCI to add-on FIFO is read in MASTER 3, the RDEMPTY output is asserted. This causes STOP to
be asserted in the MASTER 4 state. STOP asserted also prevents RDFIFO# and WRFIFO# from being asserted
and does not allow data to be transferred. When STOP is assserted, the MASTER 4 state is completes when
RDY_IN# is asserted, but the address and transfer count are not updated, and the state machine asserts
BLAST# , advancing to MASTER 7 (recovery phase). If STOP is not asserted in MASTER 4, the data phase
completes normally when RDY_IN# is asserted and the state machine advances to MASTER 5, updating the
ADDR and TXCNT registers.
The MASTER 5 data phase is identical to MASTER 4. Master 5 can be entered from either the address phase (if
the transfer count has decremented to 8) or from MASTER 4. If STOP is asserted, the state machine asserts
BLAST# and advances to MASTER 7 when RDY_IN# is asserted. If STOP is not asserted, the state machine
advances to MASTER 6 when RDY_IN# is asserted, updating the ADDR and TXCNT registers.