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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 97/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
12-17
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
Clock 2: SELECT#, byte enable, and the address
inputs remain driven to read the Pass-Thru
Data Register at offset 2Ch. PTBURST# is
asserted by the S5933, indicating the
current Pass-Thru read is a burst.
Clock 3: WR# asserted at the rising edge of clock 3
writes DATA 1 into the S5933. PTRDY#
asserted at the rising edge of clock 3
completes the current data phase.
Clock 4: Add-On logic drives DATA 2 on the Add-On
bus, but PTRDY# deasserted at the rising edge
of clock 4 extends the current data phase.
Clock 5: WR# asserted at the rising edge of clock 5
writes DATA 2 into the S5933. PTRDY#
asserted at the rising edge of clock 5
completes the current data phase.
Clock 6: Add-On logic drives DATA 3 on the Add-On
bus, but PTRDY# deasserted at the rising edge
of clock 6 extends the current data phase.
Clock 7: WR# asserted at the rising edge of clock 7
writes DATA 3 into the S5933. PTRDY#
asserted at the rising edge of clock 7
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. This is
how a PCI initiator adds wait states, if it
cannot read data quickly enough.
Clock 8: PTATN# remains deasserted at the rising
edge of clock 8. The Add-On cannot write
DATA 4 until PTATN# is asserted. Add-On
logic continues to drive DATA 4 on the
Add-On bus. PTATN# is reasserted during
the cycle, indicating the PCI initiator is
done adding wait states.
Clock 9: WR# asserted at the rising edge of clock 9
writes DATA 4 into the S5933. PTRDY#
asserted at the rising edge of clock 9
completes the current data phase.
Clock 10: Add-On logic drives DATA 5 on the Add-On
bus, but PTRDY# deasserted at the rising edge
of clock 10 extends the current data phase.
Clock 11: PTATN# remains deasserted at the rising
edge of clock 11. The Add-On does not
have to write DATA 5 until PTATN# is
asserted. Add-On logic continues to drive
DATA 5 on the Add-On bus. PTATN# is
reasserted during the cycle, indicating the
PCI initiator is done adding wait states.
Clock 12: PTRDY# asserted at the rising edge of
clock 12 completes the final data phase.
Any data written into the Pass-Thru data
register is not required and is never passed
to the PCI interface (as PTRDY# is not
asserted at the rising edge of clock 13).
Clock 13: PTATN# and PTBURST# deasserted at
the rising edge of clock 13 indicates the
Pass-Thru access is complete. The S5933
can accept new Pass-Thru accesses from
the PCI bus at clock 14.
12.2.2.5 Add-On Pass-Thru Disconnect
Operation
As discussed in Section 12.2.1.3, slow PCI targets
are prevented from degrading PCI bus performance.
The PCI specification allows only 16 clocks for a tar-
get to respond before it must request a retry on
single data phase accesses. For burst accesses, the
first data phase is allowed 16 clocks to complete, all
subsequent data phases are allowed 8 clocks each.
This requirement allows other PCI initiators to use
the bus while the target requesting the retry com-
pletes the original access.
Figure 12-8 shows the conditions that cause the
S5933 to request a retry from a PCI initiator on the
first data phase of a PCI read operation. FRAME# is
asserted during the rising edge of PCI clock 1. From
this point, the S5933 has 16 clock cycles to respond
Figure 12-8. Target Requested Retry on the First PCI Data Phase
18
17
16
15
4
3
2
1
17
16
15
14
3
2
1
PCICLK
FRAME#
STOP#
BPCLK
PTATN#
PTRDY#
PTRDY# must be asserted by
this time to present disconnecting
PTRDY# asserted too late so
S593X disconnects (asserts STOP#)
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相關(guān)代理商/技術(shù)參數(shù) |
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| S5933QC | 制造商:AMC 功能描述:IC |
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