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參數(shù)資料
| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 93/327頁(yè) |
| 文件大小： | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
12-13
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 3: SELECT#, byte enable, and the address
inputs remain driven to read the Pass-Thru
Data Register at offset 2Ch. RD# is
asserted to drive data register contents
onto the Add-On data bus.
Clock 4: Add-On logic uses the rising edge of clock 4
to store DATA 1 from the S5933. PTRDY#
asserted at the rising edge of clock 4
completes the current data phase. DATA 2
is driven on the Add-On bus.
Clock 5: Add-On logic is not fast enough to store
DATA 2 by the rising edge of clock 5.
PTRDY# deasserted at the rising edge of
clock 5 extends the current data phase and
DATA 2 remains driven on the Add-On
bus.
Clock 6: Add-On logic uses the rising edge of clock 6
to store DATA 2 from the S5933. PTRDY#
asserted at the rising edge of clock 6
completes the current data phase. DATA 3
is driven on the Add-On bus.
Clock 7: Add-On logic is not fast enough to store DATA
3 by the rising edge of clock 7. PTRDY#
deasserted at the rising edge of clock 7
extends the current data phase is and DATA
3 remains driven on the Add-On bus.
Clock 8: Add-On logic uses the rising edge of clock 8
to store DATA 3 from the S5933. PTRDY#
asserted at the rising edge of clock 8
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. Data on
the Add-On bus is not valid.
Clock 9: Because PTATN# remains deasserted,
Add-On logic cannot store data at the
rising edge of clock 9. PTATN# is reas-
serted, indicating the PCI initiator is no
longer adding wait states. DATA 4 is driven
on the Add-On bus
Clock 10: Add-On logic uses the rising edge of clock
10 to store DATA 4 from the S5933.
PTRDY# asserted at the rising edge of
clock 10 completes the current data phase.
DATA 5 is driven on the Add-On bus.
PTBURST# is deasserted, indicating that
on the PCI bus, the burst is complete
except for the last data phase. Since the
data is double buffered, there may be one
or two pieces of data available to the Add-
On when PTBURST# becomes inactive.
This example shows the single data
available case. If another piece of data was
available, then PTATN# would remain
active instead of going inactive at clock 12.
Clock 11: Add-On logic is not fast enough to store
DATA 5 by the rising edge of clock 11.
PTRDY# deasserted at the rising edge of
clock 11 extends the data phase and
DATA 5 remains driven on the Add-On
bus.
Clock 12: Add-On logic uses the rising edge of clock
12 to store DATA 5 from the S5933.
PTRDY# asserted at the rising edge of
clock 12 completes the final data phase.
Clock 13: PTATN# deasserted at the rising edge of
clock 13 indicates the Pass-Thru access is
complete. The S5933 can accept new
Pass-Thru accesses from the PCI bus at
clock 14.
12.2.2.4 Pass-Thru Burst Reads
A Pass-Thru burst read operation occurs when a PCI
initiator reads multiple DWORDs from a Pass-Thru re-
gion. A burst transfer consists of a single address and
a multiple data phases. During the address phase of
the PCI transfer, the S5933 stores the PCI address
into the Pass-Thru Address Register (APTA). If the
S5933 determines that the address is within one of its
defined Pass-Thru regions, it indicates to the Add-On
that a write to the Pass-Thru Data Register (APTD) is
required. Figure 12-6 shows a 6 data phase Pass-
Thru burst read access (Add-On write) using PTADR#.
Clock 0: PCI address information is stored in the
S5933 Pass-Thru Address Register. The
PCI address is recognized as an access to
Pass-Thru region 1. PTATN# is asserted
by the S5933 to indicate a Pass-Thru
access is occurring.
Clock 1: Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 2.
PTBURST#
Deasserted, the S5933 does
not yet recognize a PCI
burst.
PTNUM[1:0] 01. Indicates the PCI access
is to Pass-Thru region 1.
PTWR
Deasserted. The Pass-Thru
access is a read.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
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