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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 43/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
9-8
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
9.4.1 Pass-Thru Status Indicators
The Pass-Thru status indicators indicate that a Pass-
Thru access is in process and what action is required
by the Add-On logic to complete the access. All Pass-
Thru status indicators are synchronous with the PCI
clock.
9.4.2 Pass-Thru Control Inputs
Some Pass-Thru implementations may require an ad-
dress corresponding to the Pass-Thru data. The Add-
On Pass-Thru Address Register (APTA) contains the
PCI address for the Pass-Thru cycle. To allow access
to the Pass-Thru address without generating an Add-
On read cycle, PTADR# is provided. PTADR# is a
direct access input for the Pass-Thru address. Assert-
ing PTADR# is functionally identical to accessing the
Pass-Thru address register with RD#, SELECT#,
BE[3:0]#, and ADR[6:2]. RD# and WR# must be
deasserted when PTADR# is asserted, but SELECT#
may be asserted. These inputs automatically drive the
address (internally) to 28h and assert all byte enables.
The ADR[6:2] and BE[3:0]# are ignored when using
the PTADR# direct access input. When PTADR# is
asserted, the contents of the APTA register are imme-
diately driven onto the Add-On data bus.
The PTADR# direct access signal accesses the
Pass-Thru address register as 16-bits or 32-bits,
mode, PTADR# only presents the lower 16-bits of the
APTA register.
PTRDY# indicates that the Add-On has completed
the current Pass-Thru access. Multiple Add-On reads
or writes may occur to the Pass-Thru data (APTD)
register before asserting PTRDY#. This may be re-
quired for 8-bit or 16-bit Add-On interfaces using mul-
tiple accesses to the 32-bit Pass-Thru data register.
In some cases, the Add-On bus may be 32-bits, but
logic may require multiple BPCLK periods to read or
write data. In this situation, accesses may be ex-
tended by holding off PTRDY#. PTRDY# must be
synchronized to BPCLK.
9.5
NON-VOLATILE MEMORY INTERFACE
The S5933 allows read and write access to the nv
memory device used for configuration. Reads are
necessary during device initialization as configuration
information is downloaded into the S5933. If an ex-
pansion BIOS is implemented in the nv memory, the
host transfers (shadows) the code into system
DRAM. Writes are useful for in-field updates to ex-
pansion BIOS code. This allows software to update
the nv memory contents without altering hardware.
9.5.1 Non-Volatile Memory Interface Signals
For serial nv memory devices, there are only two
signals used to interface with nv memory. SCL is the
serial clock, and SDA is the serial data line. The func-
tionality of these signals is described in-detail in Sec-
tion 7.3. The designer does not need to generate the
timings for SCL and SDA. The S5933 automatically
performs the correct serial access when programmed
as described in Section 9.5.2.
For byte-wide nv memory devices, there is an 8-bit
data bus (EQ7:0), and a 16-bit address bus (EA15:0)
dedicated for the nv memory interface. When a serial
nv memory is implemented, many of these pins have
alternate functions. The S5933 also has read (ERD#)
and write (EWR#) outputs to drive the OE# and WR#
inputs on a byte-wide nv memory. The designer does
not need to generate the timings for these outputs.
The S5933 automatically performs the read and
write accesses when programmed as described in
Section 9.5.2.
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