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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 178/327頁(yè) |
| 文件大小： | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-32
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933
The MASTER 6 data phase can be entered from either the address phase (if the transfer count has
decremented to 4) or from MASTER 5. Only RDY_IN# is monitored in MASTER 6. Because MASTER 7 is the
next state anyway, there is no need to monitor STOP. BLAST# is always asserted during the MASTER 6 state.
When RDY_IN# is asserted, the state machine advances to MASTER 7, and the ADDR and TXCNT registers
are updated.
MASTER 7 is the recovery phase. In MASTER 7, RDY_IN#, RDEMPTY, WRFULL, STOP, and DONE are
monitored. DONE is an internal signal which indicates that the transfer count is zero. Based on these signals,
the state machine either returns to the idle state (MASTER 0) or starts another transfer by advancing to the
address phase (MASTER 2). If RDY_IN# is low, the state machine remains in MASTER 7. If RDY_IN# is high
and the DMA request is still active (RDEMPTY or WRFULL deasserted), the state machine advances to
MASTER 2 to begin another data transfer. If RDY_IN# is high and DONE or STOP is asserted (either the
transfer count is zero, or the FIFO cannot support another transfer yet), then the state machine returns to
MASTER 0 and relinquishes control of the add-on bus by deasserting HOLD.
2.5
DMA Controller Bus Operation
The DMA controller emulates bus cycles of an Intel 960Jx processor. This allows the controller to transfer data
directly to and from memory controllers or peripherals designed for the 960. The S5933 FIFO allows an unlimited
burst length, but the 960 supports a maximum of 4 data phases burst accesses. Therefore, the DMA controller
bursts no more than four consecutive data phases before issuing an address phases.
2.5.1
FIFO DMA Request for Writes to an Add-on Destination
For the S5933 PCI to add-on FIFO, RDEMPTY is deasserted when there is valid data in the FIFO. The FIFO can
be filled by another PCI bus initiator using the S5933 as a target, or the S5933 can fill its own FIFO by acting as
a PCI bus master. The DMA controller functions identically in either case. RDEMPTY deasserted acts as a DMA
request to the controller when RWCONT =1.
2.5.2
FIFO DMA Request for Reads from an Add-on Source
For the S5933 add-on to PCI FIFO, WRFULL is deasserted when the add-on to PCI FIFO is completely full. The
FIFO can be emptied by another PCI bus initiator using the S5933 as a target, or the S5933 can empty its own
FIFO by acting as a PCI bus master. The DMA controller functions identically in either case. WRFULL
deasserted acts as a DMA request to the controller when RWCONT=0.
2.5.3
DMA Requests and Add-on Bus Arbitration
When the DMA controller has been programmed with a source address (for DMA reads) or destination address
(for DMA writes) and a transfer byte count, it is ready to receive DMA requests from the S5933. For DMA reads
(RWCONT=1), RDEMPTY acts as the request. Whenever RDEMPTY is low, there is data in the PCI to add-on
FIFO that needs to be transferred to an add-on destination. For DMA writes (RWCONT=0), WRFULL acts as the
request. Whenever WRFULL is low there are empty locations in the add-on to PCI FIFO that need to be filled
from an add-on source. RDEMPTY or WRFULL low starts the MASTER state machine.
Figure 4 shows the sequence for the DMA controller becoming the add-on bus master. The DMA controller
becomes an add-on bus master using the 960 processor’s hold/hold acknowledge protocol. When a DMA
request is received, HOLD is asserted. When the processor returns HLDA, the DMA controller can begin
transferring data to or from the S5933 FIFO. The DMA controller remains bus master until the request is
removed (RDEMPTY or WRFULL asserted).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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