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參數(shù)資料
| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 176/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-30
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933
Figure 2 shows a register write cycle by a 960Jx processor to the DMA controller. Ta indicates the processor
address phase, Td is the data phase and Tr is the recovery phase. RDY_RCV# is an input into the 960
processor and is driven by the DMA controller RDY_OUT# signal. BLAST# is also driven by the processor and
indicates the current data phase is the last data phase of a burst. For a single-cycle access, BLAST# is asserted
during the first and only data phase.
Figure 2. Processor Write to DMA Address Register
2.4
DMA Controller Bus Master State Machine
The MASTER state machine controls transfers across the add-on bus when DMA controller is the add-on bus
master. In the idle state (MASTER 0), the controller monitors the S5933 FIFO status outputs. If the DMA
controller is programmed to read from the PCI to add-on FIFO (RWCONT=1), RDEMPTY is monitored. If the
DMA controller is programmed to write to the add-on to PCI FIFO (RWCONT=0), WRFULL is monitored.
RDEMPTY and WRFULL act as the DMA requests (and they will be referred to as ‘the DMA request’ in the
description of the MASTER state machine). Neither request will be acted upon by the DMA controller if the
transfer count register is zero. Regardless of whether the transfer is to be a read or a write, the state machine
operates the same way, only the W/R# output is different. The MASTER state machine state diagram is shown
in Figure 3. For simplicity, only the conditions required to change states are shown. All other conditions result in
the state machine remaining in the present state.
Once a valid DMA request is received (with a non-zero transfer count), the state machine advances to MASTER
1. In MASTER 1, HOLD is asserted to the add-on processor. The state machine does not advance to MASTER 2
until HLDA is returned by the processor, indicating that the DMA controller has access to the add-on bus. HLDA
asserted enables the outputs for all of the bidirectional DMA controller signals (ADS#, BLAST#, W/R#, BE3:0#).
MASTER 2 is the address phase for an add-on bus cycle. In MASTER 2, ADS# is asserted and the outputs for
the AD31:0 signals are enabled, driving the DMA transfer address on the add-on bus. The next rising edge of
BPCLK advances the state machine to one of four data phases: MASTER 3-6. Which state occurs depends on
the remaining transfer count value. Because BLAST# (last data phase of a burst indicator) is always asserted in
MASTER 6, the state machine always operates so that the final operation of a DMA transfer ends in MASTER 6.
MASTER 3 is the first data phase of a four data phase burst. If the transfer count is 16 bytes or more in the
MASTER 2 state, the state machine advances to MASTER 3 (because at least 4 more data phases are
required). If the state machine enters MASTER 3, there is always data to transfer, so only RDY_IN# is moni-
tored. The state machine remains in MASTER 3 until RDY_IN# is asserted by the add-on device being ac-
cessed. When RDY_IN# is asserted, the state machine advances to MASTER 4, and the ADDR and TXCNT
registers are updated.
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PDF描述 |
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| S5933QE | PCI BUS CONTROLLER, PQFP160 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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