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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 82/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
12-3
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
12.0 PASS-THRU OVERVIEW
The S5933 provides a simple registered access port
to the PCI bus. Using a handshaking protocol with
Add-On card logic, the PCI bus directly accesses re-
sources on the Add-On. The Pass-Thru data transfer
method is very useful for direct Add-On memory ac-
cess, or accessing registers within peripherals on an
Add-On board. Pass-Thru operation requires an ex-
ternal nv memory boot device to define and configure
the S5933 Pass-Thru regions.
The S5933 provides four user-configurable Pass-
Thru regions. Each region corresponds to a PCI Con-
figuration Base Address Register (BADR1-4). A
region represents a block of address space (the
block size is user-defined). Each block can be
mapped into memory or I/O space. Memory mapped
regions can request to be located below 1 MByte
(Real Mode address space for a PC). Each region
also has a configurable bus width for the Add-On bus
interface. An 8-, 16-, or 32-bit Add-On interface may
be selected, for use with a variety of Add-On memory
or peripheral devices.
Pass-Thru features can be used only when the
S5933 is a PCI target. As a target, the S5933 Pass-
Thru mode supports single data transfers as well as
burst transfers. When accessed with burst transfers,
the S5933 supports data transfers at the full PCI
bandwidth. The data transfer rate is only limited by
the PCI initiator performing the access and the speed
of the Add-On logic.
12.1 FUNCTIONAL DESCRIPTION
To provide the PCI bus Add-On with direct access to
Add-On resources, the S5933 has an internal Pass-
Thru Address Register (APTA), and a Pass-Thru
Data Register (APTD). These registers are con-
nected to both the PCI bus interface and the Add-On
bus interface. This allows a PCI initiator to perform
Pass-Thru writes (data transferred from the PCI bus
to the Add-On bus) or Pass-Thru reads (PCI bus re-
quests data from the Add-On bus). The S5933 Pass-
Thru interface supports both single cycle (one data
phase) and burst accesses (multiple data phases).
12.1.1 Pass-Thru Transfers
Data transfers between the PCI bus and the Add-On
using the Pass-Thru interface are implemented with a
handshaking scheme. If the PCI bus writes to an
S5933 Pass-Thru region, Add-On logic must read the
data from the S5933 and store it on the Add-On. If
the PCI bus reads from a Pass-Thru region, Add-On
logic must write data to the S5933.
Some applications may require that an address be
passed to the Add-On for Pass-Thru accesses. For
example, a 4 Kbyte Pass-Thru region on the PCI bus
may correspond to a 4 Kbyte block of SRAM on the
Add-On card. If a PCI initiator accessed this region,
the Add-On would need to know the offset within the
memory device to access. The Pass-Thru Address
Register (APTA) allows the Add-On to access ad-
dress information for the current PCI cycle. When the
PCI bus performs burst accesses, the APTA register
is updated by the S5933 to reflect the address of the
current data phase.
For PCI writes to the Add-On, the S5933 transfers
the data from the PCI bus into the Pass-Thru Data
Register (APTD). The S5933 captures the data from
the PCI bus when TRDY# is asserted. The PCI bus
then becomes available for other transfers. When the
Pass-Thru data register becomes full, the S5933 as-
serts the Pass-Thru status signals (Section 12.1.2) to
indicate to the Add-On that data is present. The Add-
On logic may read the data register and assert
PTRDY# to indicate the current access is complete.
Until the current access completes, the S5933 re-
sponds to further Pass-Thru accesses with retries.
For PCI reads from the Add-On, the S5933 asserts
the Pass-Thru status signals (Section 12.1.2) to indi-
cate to the Add-On that data is required. The Add-On
logic should write to the Pass-Thru Data Register and
assert PTRDY# to complete the access. The S5933
does not assert TRDY# to the PCI bus until PTRDY#
is asserted by Add-On logic. If the Add-On cannot
provide data quickly enough, the S5933 signals a
retry to the PCI bus. This allows the PCI bus to per-
form other tasks, rather than waiting for a slow target.
This situation is described in more detail in Section
12.2.1.3.
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| S5933QC | 制造商:AMC 功能描述:IC |
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