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| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 91/327頁(yè) |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
12-11
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
PTBURST#
Asserted. The access has a
multiple data phases.
PTNUM[1:0] 01. Indicates the PCI access
was to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru
access is a write.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 3: SELECT#, byte enables, and the address
inputs remain driven to read the Pass-Thru
Data Register at offset 2Ch. RD# is
asserted to drive data register contents
onto the DQ bus.
Clock 4: Add-On logic uses the rising edge of clock 4
to store DATA 1 from the S5933. PTRDY#
asserted at the rising edge of clock 4
completes the current data phase. DATA 2
is driven on the Add-On bus.
Clock 5: Add-On logic uses the rising edge of clock 5
to store DATA 2 from the S5933. PTRDY#
asserted at the rising edge of clock 5
completes the current data phase. DATA 3
is driven on the Add-On bus.
Clock 6: Add-On logic uses the rising edge of clock 6
to store DATA 3 from the S5933. PTRDY#
asserted at the rising edge of clock 6
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. This is
how a PCI initiator adds wait states, if it
cannot provide data quickly enough. Data
on the Add-On bus is not valid.
Clock 7: Because PTATN# remains deasserted,
Add-On logic cannot store data at the
rising edge of clock 7. PTATN# is reas-
serted, indicating the PCI initiator is no
longer adding wait states. DATA 4 is driven
on the Add-On bus.
Clock 8: Add-On logic uses the rising edge of clock 8
to store DATA 4 from the S5933. PTRDY#
asserted at the rising edge of clock 8
completes the current data phase. On the
PCI bus, IRDY# has been deasserted
again, causing PTATN# to be deasserted.
Data on the Add-On bus is not valid.
Clock 9: The PCI initiator is still adding wait states.
Add-On logic cannot store data while
PTATN# is deasserted.
Clock 10: Because PTATN# remains deasserted,
Add-On logic cannot read data at the rising
edge of clock 10. PTATN# is reasserted,
indicating the PCI initiator is no longer
adding wait states. DATA 5 is driven on the
Add-On bus.
Clock 11: Add-On logic uses the rising edge of clock
11 to store DATA 5 from the S5933.
PTRDY# asserted at the rising edge of
clock 11 completes the current data phase.
DATA 6 is driven on the Add-On bus.
Clock 12: Add-On logic uses the rising edge of clock
12 to store DATA 6 from the S5933.
PTRDY# asserted at the rising edge of
clock 12 completes the final data phase
Clock 13: PTATN# and PTBURST# deasserted at
the rising edge of clock 13 indicates the
Pass-Thru access is complete. The S5933
can accept new Pass-Thru accesses from
the PCI bus at clock 15.
Figure 12-5 also shows a 5 data phase Pass-Thru
burst write, but the Add-On logic uses PTRDY# to
control the rate at which data is transferred. In many
applications, Add-On logic is not fast enough to ac-
cept data at every BPCLK rising edge (every 30 ns in
a 33 MHz PCI system). In this example, the Add-On
interface accepts data every other clock. In the ex-
ample, RD# is asserted during the entire Add-On
burst, but it can be deasserted when PTRDY# is
deasserted, the S5933 functions the same under
both conditions.
Clock 0: PCI address information is stored in the
S5933 Pass-Thru Address Register.
Clock 1: The PCI address is recognized as an
access to Pass-Thru region 1. PCI data for
the first data phase is stored in the S5933
Pass-Thru Data Register. PTATN# is
asserted by the S5933 to indicate a Pass-
Thru access is occurring.
Clock 2: Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 2.
PTBURST#
Asserted. The access has
multiple data phases.
PTNUM[1:0] 01. Indicates the PCI access
is to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru
access is a write.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
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