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參數(shù)資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 156/327頁 |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-12
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
3.6.1
Transfer Count Interrupts
Transfer count interrupts may come from two
sources: read transfer count and/or write transfer
count. One or both interrupts may be enabled, or
both may be disabled. A read transfer count interrupt
is generated when the Master Read Transfer Count
Register (MRTC) decrements to zero. A write trans-
fer count interrupt is generated when the Master
Write Transfer Count Register (MWTC) decrements
to zero. These registers decrement when a PCI
transfer completes successfully.
If add-on initiated DMA transfers are used with transfer
counts disabled, these interrupt sources are disabled.
3.6.2
PCI Bus Error Condition Interrupts
In some situations, the PCI bus may signal an error
condition during an S5933 DMA transfer. These error
conditions include a target abort or master abort on
the PCI bus. If one of these conditions exists, it is
important to notify the device which initiated the trans-
fer that it cannot complete successfully. Interrupts on
PCI error conditions are only enabled if one or both of
the transfer count interrupts are enabled. There is no
individual enable bit for PCI error interrupts.
A PCI target abort indicates an error condition where
no number of retries to the target will result in a
successful data transfer. A PCI master abort occurs
when a PCI bus master (the S5933, in this case)
attempts to access a PCI target which is either non-
existent or disabled. In either of these situations, the
device which set up the DMA transfer is notified with
an interrupt (either INTA# or IRQ#).
3.6.3
Controlling S5933 DMA Interrupts
For PCI initiated DMA transfers, interrupts are en-
abled through the S5933 Interrupt Control Status
Register (INTCSR). This register is located at offset
38h in the S5933 PCI Operation Registers. INTCSR is
also accessed during interrupt service routines to de-
termine the interrupt source and clear the interrupt.
The following INTCSR bits relate to DMA Operations:
Bit 14 Enable Interrupt on Write Transfer
Complete. If set, INTA# is generated
when MWTC decrements to zero during a
DMA transfer.
Bit 15 Enable Interrupt on Read Transfer
Complete. If set, INTA# is generated
when MRTC decrements to zero during a
DMA transfer.
Bit 18 Write Transfer Complete Interrupt.
When set, this bit indicates MWTC has
decremented to zero and INTA# has been
asserted. Writing a one to this bit clears
the interrupt source and deasserts INTA#.
Writing a zero to this bit has no effect.
Bit 19 Read Transfer Complete Interrupt.
When set, this bit indicates MRTC has
decremented to zero and INTA# has been
asserted. Writing a one to this bit clears
the interrupt source and deasserts INTA#.
Writing a zero to this bit has no effect.
Bit 20 Master Abort Interrupt. When set, this
bit indicates that the S5933 had to
perform a master abort and INTA# has
been asserted. Writing a one to this bit
clears the interrupt source and deasserts
INTA#. Writing a zero to this bit has no
effect.
Bit 21 Target Abort Interrupt. When set, this bit
indicates that the S5933 received a target
abort and INTA# has been asserted.
Writing a one to this bit clears the inter-
rupt source and deasserts INTA#. Writing
a zero to this bit has no effect.
For add-on initiated DMA transfers, interrupts are en-
abled through the S5933 Add-on Interrupt Control/Sta-
tus Register (AINT). This register is located at offset
38h in the S5933 Add-on Operation Registers. AINT is
also accessed during interrupt service routines to de-
termine the interrupt source and clear the interrupt. The
following AINT bits relate to DMA Operations:
Bit 14 Enable Interrupt on Write Transfer
Complete. If set, IRQ# is generated when
MWTC decrements to zero during a DMA
transfer.
Bit 15 Enable Interrupt on Read Transfer
Complete. If set, IRQ# is generated when
MRTC decrements to zero during a DMA
transfer.
Bit 18 Write Transfer Complete Interrupt.
When set, this bit indicates MWTC has
decremented to zero and IRQ# has been
asserted. Writing a one to this bit clears
the interrupt source and deasserts IRQ#.
Writing a zero to this bit has no effect.
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相關代理商/技術參數(shù) |
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| S5933QC | 制造商:AMC 功能描述:IC |
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