參數(shù)資料
型號： S29PL-J60BAW011
廠商： Spansion Inc.
元件分類： DRAM
英文描述： CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述： CMOS 3V電壓供電，同步讀/寫Flash存儲器并有增強VersatileIO控制
文件頁數(shù)： 54/96頁
文件大?。?/td> 827K
代理商： S29PL-J60BAW011
52
S29PL-J
S29PL-J_00_A9 September 22, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
13.7
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes. In addition, the following hardware data protection measures prevent accidental
erasure or programming, which might otherwise be caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system noise.
13.7.1
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets to the read mode. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The
system must provide the proper signals to the control pins to prevent unintentional writes when V
CC
is greater
than V
LKO
.
13.7.2
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE#, (CE1#, CE2# in PL129J) or WE# do not initiate a write
cycle.
13.7.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# (CE1# = CE2# in PL129J)= V
IH
or WE# =
V
IH
. To initiate a write cycle, CE# (CE1# / CE2# in PL129J) and WE# must be a logical zero while OE# is a
logical one.
13.7.4
Power-Up Write Inhibit
If WE# = CE# (CE1#, CE2# in PL129J) = V
IL
and OE# = V
IH
during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on
power-up.
14. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data. The system can read CFI information at the addresses
given in
Table 14.1 on page 53
to
Table 14.4 on page 54
. To terminate reading CFI data, the system must
write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded
Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in
Table 14.1
to
Table 14.4
. The system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales
office for copies of these documents.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29PL-J60BAW012 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
S29PL-J60BAW013 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
S29PL-J60BAW020 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
S29PL-J60BAW021 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
S29PL-J60BAW022 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
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