參數(shù)資料
型號(hào)： S29PL-J60BAW011
廠商： Spansion Inc.
元件分類： DRAM
英文描述： CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述： CMOS 3V電壓供電，同步讀/寫Flash存儲(chǔ)器并有增強(qiáng)VersatileIO控制
文件頁數(shù)： 22/96頁
文件大?。?/td> 827K
代理商： S29PL-J60BAW011
20
S29PL-J
S29PL-J_00_A9 September 22, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
10. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is a latch used to store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device.
Table 10.1
lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V, V
HH
= 8.5–9.5
V, X = Don’t Care, SA = Sector Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
High Voltage Sector
Protection on page 48
.
2. WP#/ACC must be high when writing to upper two and lower two sectors.
10.1
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE# pins (For PL129J -
CE1#/CE2# pins) to V
IL
. In PL129J, CE1# and CE2# are the power control and select the lower (CE1#) or
upper (CE2#) halves of the device. CE# is the power control. OE# is the output control and gates array data
to the output pins. WE# should remain at V
IH
.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for
read access until the command register contents are altered.
Refer to
Table 21.3 on page 84
for timing specifications and to
Figure 20.3 on page 74
for the timing
diagram. I
CC1
in the DC Characteristics table represents the active current specification for reading array
data.
Table 10.1
PL127J Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Amax–A0)
DQ15–
DQ0
Read
L
L
H
H
X
A
IN
D
OUT
Write
L
H
L
H
X
(Note 2)
A
IN
D
IN
Standby
V
IO
±
0.3 V
X
X
V
IO
±
0.3 V
X
(Note 2)
X
High-Z
Output Disable
L
H
H
H
X
X
High-Z
Reset
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect
(High Voltage)
X
X
X
V
ID
X
A
IN
D
IN
Table 10.2
PL129J Device Bus Operations
Operation
CE1#
CE2#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A21–A0)
DQ15–
DQ0
Read
L
H
L
H
H
X
A
IN
D
OUT
H
L
Write
L
H
H
L
H
X
(Note 2)
A
IN
D
IN
H
L
Standby
V
±
0.3 V
V
±
0.3 V
X
X
V
±
0.3 V
X
X
High-Z
Output Disable
L
L
H
H
H
X
X
High-Z
Reset
X
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect
(High Voltage)
X
X
X
X
V
ID
X
A
IN
D
IN
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