參數(shù)資料
型號: S1D13706F00A
元件分類: 顯示控制器
英文描述: 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝: TQFP-100
文件頁數(shù): 81/171頁
文件大?。?/td> 4940K
代理商: S1D13706F00A
APPENDIX
Appendix 3. Control registers
7751 Group User’s Manual
20–20
Timer Mode
b7
b0 b7
b0
(b15)
(b8)
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Functions
Bit
At reset
RW
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
Undefined
RW
Gate function select bits
Pulse output function select bit
1
Operating mode select bits
Bit name
Functions
b7 b6 b5
b4 b3
b2 b1 b0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
0 0 : Timer mode
0 : No pulse output
(TAiOUT pin functions as a programmable
I/O port.)
1 : Pulse output
(TAiOUT pin functions as a pulse output
pin.)
0 0 : f2 / f4
0 1 : f16 / f32
1 0 : f64 / f128
1 1 : f512 / f1024
b7 b6
Count source select bits
b1 b0
b4 b3
0
0 0 : No gate function
0 1 :
(TAiIN pin functions as a prog-
rammable I/O port.)
1 0 : Counter counts only while TAiIN
pin’s input signal is “L” level.
1 1 : Counter counts only while TAiIN
pin’s input signal is “H” level.
Bit
4
At reset
RW
0
2
0
RW
0
RW
0
RW
3
0
RW
0
RW
5
0
RW
6
7
0
RW
0
RW
0
Fix this bit to “0” in the timer mode.
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