參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 142/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
APPENDIX
7751 Group User’s Manual
20–75
Appendix 9. Q & A
Interrupt
Q
(1)
In both the edge sense and level sense, external interrupt requests occur when the input
____
signal to the INTi pin changes its level regardless of clock
φ1.
In the edge sense, the interrupt request bit is set to “1” at this time.
(2)
There are two methods: one uses external interrupt’s level sense, and the other uses the
timer’s event counter mode.
Using external interrupt’s level sense
____
In hardware, input a logical sum of multiple interrupt signals (e.g., ‘a(chǎn)’, ‘b’, and ‘c’) to the INTi
pin, and input each signal to each corresponding port.
___
In software, check the port’s input levels in the INTi interrupt routine to determine that which
of the signals ‘a(chǎn)’, ‘b’, and ‘c’ is input.
A
(1)
____
Which timing of clock
φ1 is the external interrupts (input signals to the INTi pin) detected?
(2)
____
How can four or more external interrupt input pins (INTi) be used?
Using timer’s event counter mode
In hardware, input interrupt signals to the TAiIN pins or TBiIN pins.
In software, set the timer’s operating mode to the event counter mode and a value “000016”
into the timer register to the effective edge.
The timer’s interrupt request occurs when an interrupt signal (selected effective edge) is input.
M37751
Port
INTi
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