參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 50/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
FLASH MEMORY VERSION
7751 Group User’s Manual
19–26
19.2 Serial input/output mode
q Program command
Figure 19.2.3 shows the program command execution timing.
The command code “4016” is input at the first transfer.
The low–order 8 bits and the high–order 8 bits of the address are input at the second and third
transfer.
The data is input at the forth transfer.
Programming is started at the last rising edge of the forth transfer serial clock and the BUSY signal
becomes “H” level. The input data is programmed to the specified address (input address) within
10 s as measured by the built–in timer and the BUSY signal becomes “L” level. Programming is
performed by the byte unit.
Note: Be sure to execute a program verify command after executing the program command. If this
verification fails, execute repeatedly the program and program verify commands until the
verification passes. (Refer to “19.2.4 Program algorithm flow chart.”)
Fig. 19.2.3 Program command execution timing
00
tCH
Command code input (4016)
000 00
1
Program address input
(Low-order)
A0
A7
A8
A15
D0
D7
Program data input
Program
tCH
tPC
tWP
SCLK
SDA
OE
BUSY
“H”
Program address input
(High-order)
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