參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 128/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
7751 Group User’s Manual
20–62
APPENDIX
Appendix 8. Examples of noise immunity improvement
(2)
Wiring for clock input/output pins
Make the length of wiring connected to the clock input/output pins as short as possible.
Make the length of wiring between the grounding lead of the capacitor, which is connected to
the oscillator and Vss pin of the microcomputer, as short as possible (within 20 mm).
Separate the Vss pattern for oscillation from all other Vss patterns. (Refer to Figure 14.)
Reason:
The microcomputer’s operation
synchronizes with a clock generated
by the oscillation circuit.
If noise enters clock I/O pins, clock
waveforms may be deformed. This
may cause a malfunction or a
program runaway.
Also, if the noise causes a potential
difference between the Vss level
of the microcomputer and the Vss
level of an oscillator, the correct
clock will not be input in the
microcomputer.
(3)
Wiring for CNVss pin
Connect CNVss pin to Vss pin with the shortest possible wiring.
Reason:
The processor mode of the
microcomputer is influenced by a
potential at CNVss pin when
CNVss
and
Vss
pins
are
connected.
If the noise causes a potential
difference between CNVss and
Vss pins, the processor mode may
become unstable. This may cause
a microcomputer malfunction or
a program runaway.
Fig. 6. Wiring for clock input/output pins
Fig. 7. Wiring for CNVss pin
Noise
XIN
XOUT
Vss
XIN
XOUT
Vss
M37751
Not acceptable
Acceptable
Noise
CNVss
Vss
M37751
CNVss
Vss
M37751
Acceptable
Not Acceptable
q
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相關代理商/技術參數(shù)
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