參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 21/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
Page 22
Epson Research and Development
Vancouver Design Center
S1D13706
Hardware Functional Specification
X31B-A-001-06
Issue Date: 01/02/23
BS#
I
8
LIS
HIOVDD
1
This input pin has multiple functions.
For Generic #1, this pin must be tied to IO VDD.
For Generic #2, this pin must be tied to IO VDD.
For SH-3/SH-4, this pin inputs the bus start signal (BS#).
For MC68K #1, this pin inputs the address strobe (AS#).
For MC68K #2, this pin inputs the address strobe (AS#).
For REDCAP2, this pin must be tied to IO VDD.
For DragonBall, this pin must be tied to IO VDD.
summary.
RD/WR#
I
12
LIS
HIOVDD
1
This input pin has multiple functions.
For Generic #1, this pin inputs the read command for the
upper data byte (RD1#).
For Generic #2, this pin must be tied to IO VDD.
For SH-3/SH-4, this pin inputs the RD/WR# signal. The
S1D13706 needs this signal for early decode of the bus cycle.
For MC68K #1, this pin inputs the R/W# signal.
For MC68K #2, this pin inputs the R/W# signal.
For REDCAP2, this pin inputs the R/W signal.
For DragonBall, this pin must be tied to IO VDD.
summary.
RD#
I
9
LIS
HIOVDD
1
This input pin has multiple functions.
For Generic #1, this pin inputs the read command for the lower
data byte (RD0#).
For Generic #2, this pin inputs the read command (RD#).
For SH-3/SH-4, this pin inputs the read signal (RD#).
For MC68K #1, this pin must be tied to IO VDD.
For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
For REDCAP2, this pin inputs the output enable (OE).
For DragonBall, this pin inputs the output enable (OE).
summary.
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
Voltage
RESET#
State
Description
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