參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 46/171頁
文件大小： 4940K
代理商： S1D13706F00A
FLASH MEMORY VERSION
7751 Group User’s Manual
19–23
19.2 Serial input/output mode
19.2.2 Access to built–in flash memory
Figure 19.2.1 shows the pin connection in the serial I/O mode.
___
When inputting “H” level to the SDA (P45), SCLK (P46), and OE signal input (P51) pins, and after that,
applying the VPPH level to the VPP (CNVSS), the built–in flash memory operates in the serial I/O mode. The
software command, address, and data required for operation of the built–in flash memory are input/output
by the clock synchronous serial transfer in this mode. The software command, address, and program data
are taken from SDA pin to the inside synchronously with the rising edge of the serial clock inputting to
SCLK pin. The read data, verify data, and error code are externally output from SDA pin synchronously
with the falling edge of the serial clock. The transfer is performed at 8–bit length and LSB first.
In the serial I/O mode, the built–in flash memory is accessed by inputting (execution) of the software
command. Table 19.2.2 lists the software command. To execute the software command requires twice or
four times of the transfer. In the first transfer, the command code is input for selecting the built–in flash
memory’s operation. In the second to fourth transfer, address and data etc. are input/output.
Each software command is described below.
As the capacity of the built-in flash memory is 48 Kbytes, specify addresses 400016 to FFFF16. If the
addresses except addresses 400016 to FFFF16 are specified, the error occurs.
Table 19.2.2 Software command and input/output information
First transfer
(command code input)
0016
4016
C016
3016
8016
Software command
Read
Program
Program verify
Auto erase
Error check
Second transfer
Low-order 8 bits of
read address input
Low-order 8 bits of
program address input
Verify data output
3016 (command
code) input
Error code output
Third transfer
High-order 8 bits of
read address input
High-order 8 bits of
program address input
Forth transfer
Read data output
Program data input
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