參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 67/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
APPENDIX
Appendix 2. Memory assignment in SFR area
7751 Group User’s Manual
20–8
Timer A0 interrupt control register
Timer A1 interrupt control register
UART1 receive interrupt control register
UART0 transmit interrupt control register
Access characteristics
State immediately after a reset
Watchdog timer frequency select register
6016
6116
6216
6316
6416
6516
6616
6716
6816
6916
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
7D16
7E16
7F16
6B16
6C16
6D16
6E16
6F16
6A16
RW
b7
b0
(Note 1)
RW
0
00
0
?
0
? (Note 2)
b7
b0
0
00
0
00
0
00
0
RW
00
0
00
0
00
0
00
0
00
0
00
0
00
0
00
0
00
0
00
0
00
0
RW
Address
A-D conversion interrupt control register
UART1 transmit interrupt control register
INT2 interrupt control register
Register name
Watchdog timer register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
Timer B0 interrupt control register
INT1 interrupt control register
Notes 1: By writing dummy data to address 6016, a value “FFF16” is set to the watchdog timer. The
dummy data is not retained anywhere.
2: The value “FFF16” is set tot the watchdog timer. (Refer to “Chapter 9. WATCHDOG TIMER.”)
UART0 receive interrupt control register
?
: It is possible to read the bit state at reading. The written value becomes valid data.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
RW
RO
WO
Access characteristics
: “0” immediately after a reset.
: “1” immediately after a reset.
: Undefined immediately after
a reset.
0
1
?
: Always “0” at reading
0
: Always undefined at reading
: “0” immediately after a reset. Fix this bit to “0.”
?
State immediately after a reset
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