參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 140/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
APPENDIX
7751 Group User’s Manual
20–73
Appendix 9. Q & A
Interrupt
There is a routine where a certain interrupt request should not be accepted (with enabled acceptance
of all other interrupt requests). Accordingly, the program set the interrupt priority level select bits of
the interrupt to be not accepted to “0002” in order to disable it before executing the routine. However,
the interrupt request of that interrupt has been accepted immediately after the priority level had been
changed. Why did this occur and what can I do about it?
When changing the interrupt priority level, the microcomputer can behave “as if the interrupt request
is accepted immediately after it is disabled ” if the next instruction (the LDA instruction in the above
case) is already stored in the BIU’s instruction queue buffer and conditions to accept the interrupt
request which should not be accepted are met immediately before executing the instruction which is
in that buffer.
When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the
CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into
the actual address. Detection of interrupt priority level is performed at the beginning of each instruc-
tion.
In the above case, in the interrupt priority detection which is performed simultaneously with the
execution of the next instruction, the interrupt priority level before changing it is detected and the
interrupt request is accepted. It is because the CPU executes the next instruction before the BIU
finishes changing the interrupt priority levels.
Q
A
(1/2)
Interrupt request is
accepted
in
this
interval
:
LDM #00H, XXXIC ; Writes “0002” to interrupt priority level select bits.
; Clears interrupt request bit to “0.”
LDA A,DATA
; Instruction at the beginning of the routine that
should not accept one certain interrupt request.
:;
Previous instruction
executed
(Instruction prefetch)
CPU operation
BIU operation
Interrupt priority detection time
Sequence of execution
Interrupt priority level select bits set
Change of interrupt priority levels
completed
Interrupt request accepted
Interrupt request generated
LDM instruction
executed
LDA instruction
executed
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