參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 66/171頁
文件大小： 4940K
代理商： S1D13706F00A
APPENDIX
7751 Group User’s Manual
20–7
Appendix 2. Memory assignment in SFR area
5C16
Timer B1 mode register
0
4016
4116
4216
4316
4416
4516
4616
4716
4816
4916
5016
5116
5216
5316
5416
5516
5616
5716
5816
5916
5A16
5B16
5D16
5E16
5F16
4B16
4C16
4D16
4E16
4F16
4A16
WO
V
RW
V
b7
b0
RW
V
RW
WO
RW
?
0016
?
0016
b7
b0
?
0016
00
??
0
00
0
??
0
WO
RW
V
RW
00
0
??
0
00
0
00
0
RW
00
0
: It is possible to read the bit state at reading. The written value becomes valid data.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
RW
RO
WO
Access characteristics
: “0” immediately after a reset.
: “1” immediately after a reset.
: Undefined immediately after
a reset.
0
1
?
: Always “0” at reading
0
: Always undefined at reading
: “0” immediately after a reset. Fix this bit to “0.”
?
State immediately after a reset
Register name
Address
Access characteristics
State immediately after a reset
Timer B2 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Processor mode register 0
One-shot start register
Timer A0 register
Up-down register
Timer A1 register
Count start register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer B0 mode register
Timer B2 mode register
Timer A0 mode register
Timer A4 mode register
Processor mode register 1
?
V
V The access characteristics at addresses 4616 to 4F16 varies according to Timer A’s operating mode.
(Refer to “Chapter 5. TIMER A.”)
V The access characteristics at addresses 5016 to 5516 varies according to Timer B’s operating mode.
(Refer to “Chapter 6. TIMER B.”)
V The access characteristics of bit 5 at addresses 5B16 to 5D16 varies according to Timer B’s operating
mode. (Refer to “Chapter 6. TIMER B.”)
V The access characteristics of bit 1 at address 5E16 and its state immediately after a reset vary according
to the voltage level supplied to the CNVSS pin. (Refer to section “2.5 Processor modes.”)
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