參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 76/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
APPENDIX
Appendix 3. Control registers
7751 Group User’s Manual
20–16
UARTi transmit/receive control register 1
UARTi receive buffer register
Bit
Bit name
At reset
5
Framing error flag
(Valid in UART mode)
0
0 : No framing error
1 : Framing error detected
RW
Functions
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Notes 1: Bit 4 is cleared to “0” when clearing the receive enable bit to “0.”
Bits 5 and 6 are cleared to “0” when one of the following is performed:
clearing the receive enable bit to “0.”
reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out.
Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.”
2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode.
0
Transmit enable bit
0
0 : Transmission disabled
1 : Transmission enabled
1
Transmit buffer empty flag
1
0 : Data present in transmit buffer
register.
1 : No data present in transmit
buffer register.
2
Receive enable bit
0
0 : Reception disabled
1 : Reception enabled
3
Receive complete flag
0
0 : No data present in receive
buffer register.
1 : Data present in receive buffer
register.
4
Overrun error flag
0
0 : No overrun error
1 : Overrun error detected
6
Parity error flag
(Valid in UART mode)
0
0 : No parity error
1 : Parity error detected
7
Error sum flag
(Valid in UART mode)
0
0 : No error
1 : Error detected
(Notes 1, 2)
(Note 1)
RW
RO
RW
RO
b7
b0
Bit
8 to 0
At reset
Undefined
RW
Functions
RO
b7
b0
(b15)
(b8)
15 to 9
–
UART0 receive buffer register (Addresses 3716, 3616)
UART1 receive buffer register (Addresses 3F16, 3E16)
Nothing is assigned.
The value is “0” at reading.
Receive data is read out from here.
0
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