參數(shù)資料
型號: S1D13706F00A
元件分類: 顯示控制器
英文描述: 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝: TQFP-100
文件頁數(shù): 26/171頁
文件大小: 4940K
代理商: S1D13706F00A
Page 26
Epson Research and Development
Vancouver Design Center
S1D13706
Hardware Functional Specification
X31B-A-001-06
Issue Date: 01/02/23
4.3.3 Clock Input
4.3.4 Miscellaneous
4.3.5 Power And Ground
Table 4-4: Clock Input Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
Voltage
RESET#
State
Description
CLKI
I
15
LI
NIOVDD
Typically used as input clock source for bus clock and memory
clock
CLKI2
I
77
LI
NIOVDD
Typically used as input clock source for pixel clock
Table 4-5: Miscellaneous Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
Voltage
RESET#
State
Description
CNF[7:0]
I
78-85
LI
NIOVDD
These inputs are used to configure the S1D13706 - see Table 4-7:
Note: These pins are used for configuration of the S1D13706
and must be connected directly to IO VDD or VSS.
GPO
O
47
LO3
NIOVDD
0
General Purpose Output (possibly used for controlling the LCD
power). It may also be used for the MOD control signal of the Sharp
HR-TFT panel.
TESTEN
I
86
T1
NIOVDD
0
Test Enable input used for production test only (has type 1 pull-
down resistor with a typical value of 50
at 3.3V).
Table 4-6: Power And Ground Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
Voltage
RESET#
State
Description
HIOVDD
P
16, 26
P
——
IO VDD pins associated with the host interface pins as described in
NIOVDD
P
37, 49,
63, 76
P
——
IO VDD pins associated with the non-host interface pins as
COREVDD
P
1, 51
P
——
2 Core VDD. pins.
VSS
P
14, 25,
36, 50,
62, 75,
100
P
——
7 VSS pins.
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