參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 22/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
Epson Research and Development
Page 23
Vancouver Design Center
Hardware Functional Specification
S1D13706
Issue Date: 01/02/23
X31B-A-001-06
WAIT#
O
17
LB2A
HIOVDD
Hi-Z
During a data transfer, this output pin is driven active to force the
system to insert wait states. It is driven inactive to indicate the
completion of a data transfer. WAIT# is released to the high
impedance state after the data transfer is complete. Its active
polarity is configurable. See Table 4-7: “Summary of Power-
For Generic #1, this pin outputs the wait signal (WAIT#).
For Generic #2, this pin outputs the wait signal (WAIT#).
For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
For SH-4 mode, this pin outputs the device ready signal
(RDY#).
For MC68K #1, this pin outputs the data transfer acknowledge
signal (DTACK#).
For MC68K #2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#).
For REDCAP2, this pin is unused (Hi-Z).
For DragonBall, this pin outputs the data transfer acknowledge
signal (DTACK).
summary.
RESET#
I
13
LIS
HIOVDD
0
Active low input to set all internal registers to the default state and
to force all signals to their inactive states.
Table 4-2: Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
IO
Voltage
RESET#
State
Description
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